Michael Hutton - researchr alias

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Viewing Publication 1 - 6 from 6

2007

Efficient Timing Analysis With Known False Paths Using Biclique CoveringShuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Michael Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris, Chung-Kuan Cheng. tcad, 26(5):959-969, 2007. [doi]

2006

A methodology for FPGA to structured-ASIC synthesis and verificationMichael Hutton, Richard Yuan, Jay Schleicher, Gregg Baeckler, Sammy Cheung, Kar Keng Chua, Hee Kong Phoo. date 2006: 64-69 [doi]

Efficient static timing analysis using a unified framework for false paths and multi-cycle pathsShuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael Hutton. aspdac 2006: 73-78 [doi]

2005

Improving the efficiency of static timing analysis with false pathsShuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris. iccad 2005: 527-531

2004

Improving FPGA Performance and Area Using an Adaptive Logic ModuleMichael Hutton, Jay Schleicher, David M. Lewis, Bruce Pedersen, Richard Yuan, Sinan Kaptanoglu, Gregg Baeckler, Boris Ratchev, Ketan Padalia, Mark Bourgeault, Andy Lee, Henry Kim, Rahul Saini. fpl 2004: 135-144 [doi]

2002

Interconnect enhancements for a high-speed PLD architectureMichael Hutton, Vinson Chan, Peter Kazarian, Victor Maruri, Tony Ngai, Jim Park, Rakesh Patel, Bruce Pedersen, Jay Schleicher, Sergey Shumarayev. fpga 2002: 3-10 [doi]

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