Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability - researchr publication

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Michael Kessler, Gundolf Kiefer, Jens Leenstra, Knut Schünemann, Thomas Schwarz, Hans-Joachim Wunderlich. Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability. In Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October - 1 November 2001. pages 461-469, IEEE Computer Society, 2001.

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