Debajit Bhattacharya - researchr alias

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Viewing Publication 1 - 7 from 7

2017

Analytical Modeling of the SMART NoCDebajit Bhattacharya, Niraj K. Jha. tmscs, 3(4):242-254, 2017. [doi]

2016

TCAD-Assisted Capacitance Extraction of FinFET SRAM and Logic ArraysDebajit Bhattacharya, Niraj K. Jha. tvlsi, 24(1):329-333, 2016. [doi]

Ultra-High Density Monolithic 3-D FinFET SRAM With Enhanced Read StabilityDebajit Bhattacharya, Niraj K. Jha. tcas, 63-I(8):1176-1187, 2016. [doi]

Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up MechanismSourindra Chaudhuri, Ajay N. Bhoj, Debajit Bhattacharya, Niraj K. Jha. vlsid 2016: 300-305 [doi]

2015

Design of Efficient Content Addressable Memories in High-Performance FinFET TechnologyDebajit Bhattacharya, Ajay N. Bhoj, Niraj K. Jha. tvlsi, 23(5):963-967, 2015. [doi]

2014

TCAD structure synthesis and capacitance extraction of a voltage-controlled oscillator using automated layout-to-device synthesis methodologyDebajit Bhattacharya, Rajiv V. Joshi, Herschel A. Ainspan, Ninad D. Sathaye, Mohit Bajaj, Suresh Gundapaneni, Niraj K. Jha. cicc 2014: 1-4 [doi]

2013

Design and Implementation of a High-Speed, Power-Efficient, Modified Hybrid-Mode Sense Amplifier for SRAM ApplicationsDebajit Bhattacharya, Ashis Maity, Amit Patra. vlsid 2013: 209-214 [doi]

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