Takato Katayama, Shiko Miyashita, Kazuki Sobue, Koichi Hamashita. A 1.25MS/S Two-Step Incremental ADC with 100DB DR and 110DB SFDR. In 2018 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, June 18-22, 2018. pages 205-206, IEEE, 2018. [doi]
Abstract is missing.