Takato Katayama, Shiko Miyashita, Kazuki Sobue, Koichi Hamashita. A 1.25MS/S Two-Step Incremental ADC with 100DB DR and 110DB SFDR. In 2018 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, June 18-22, 2018. pages 205-206, IEEE, 2018. [doi]
@inproceedings{KatayamaMSH18,
title = {A 1.25MS/S Two-Step Incremental ADC with 100DB DR and 110DB SFDR},
author = {Takato Katayama and Shiko Miyashita and Kazuki Sobue and Koichi Hamashita},
year = {2018},
doi = {10.1109/VLSIC.2018.8502298},
url = {https://doi.org/10.1109/VLSIC.2018.8502298},
researchr = {https://researchr.org/publication/KatayamaMSH18},
cites = {0},
citedby = {0},
pages = {205-206},
booktitle = {2018 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, June 18-22, 2018},
publisher = {IEEE},
isbn = {978-1-5386-4214-6},
}