Abstract is missing.
- A 3.2 GHz 178fsrms Jitter Injection Locked Clock Multiplier Using Sub-Sampling FTL and DLL for In-Band Noise ImprovementDong Hyun Yoon, Dong-Kyu Jung, Kiho Seong, Tae-Hyeok Eom, Jae-Soub Han, Ju Eon Kim, Tony Tae-Hyoung Kim, Kwang-Hyun Baek. 1-3 [doi]
- A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN AccelerationChih-Sheng Lin, Fu-Cheng Tsai, Jian-Wei Su, Sih-Han Li, Tian-Sheuan Chang, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Chih-I Wu, Tuo-Hung Hou. 1-3 [doi]
- 2 VCO-Based Delta Sigma Modulator with Digital Tri-level Feedback SchemeJue Wang, Zhenyu Yang, Jiawei Wang, Xu Cheng 0002, Jun Han 0003, Xiaoyang Zeng. 1-3 [doi]
- 245/243GHz, 9.2/10.5dBm Saturated Output Power, 4.6/2.8% PAE, and 28/26dB Gain Power Amplifiers in 65nm CMOS Adopting 2-and 4-way Power CombiningByeonghun Yun, Dae-Woong Park, Kyung-Sik Choi, Ho-Jin Song, Sang-Gug Lee. 1-3 [doi]
- A 40nm Embedded SG-MONOS Flash Macro for High-end MCU Achieving 200MHz Random Read Operation and 7.91Mb/mm2 Density with Charge Assisted Offset Cancellation Sense AmplifierMasaya Nakano, Yoshinobu Kaneda, Koichi Takeda, Takahiro Shimoi, Yasunobu Aoki, Satoru Nakanishi, Yosuke Tashiro, Yasuhiko Taito, Ken Matsubara, Munekatsu Nakagawa, Tomoya Ogawa, Takashi Kurafuji, Hidenori Mitani, Takashi Ito, Takashi Kono. 1-3 [doi]
- A 33.5-37.5 GHz 4-Element Phased-Array Transceiver Front-End with High-Accuracy Low-Variation 6-bit Resolution 360° Phase Shift and 0~31.5 dB Gain Control in 65 nm CMOSPingda Guan, Haikun Jia, Wei Deng 0001, Zhihua Wang 0001, Baoyong Chi. 1-3 [doi]
- Energy-efficient charge sharing-based 8T2C SRAM in-memory accelerator for binary neural networks in 28nm CMOSHyunmyung Oh, HyungJun Kim, Daehyun Ahn, JiHoon Park, Yulhwa Kim, Inhwan Lee, Jae-Joon Kim. 1-3 [doi]
- A 1280 x 720 Micro-LED Display Driver with 10-Bit Current-Mode Pulse Width ModulationPei-Yi Lai Lee, Ya-Wen Yang, Sih-Han Li, Jian-Jhih Sun, Tzu-Yi Hung, Chih-Wen Lu, Yen-Hsiang Fang, Wei-Hung Kuo, Li-Chun Huang, Guo-Dung John Su, Poki Chen. 1-3 [doi]
- -6Jiahao Liu, Yan Zhu 0001, Chi-Hang Chan, Rui Paulo Martins. 1-3 [doi]
- An Energy-Efficient Deep Reinforcement Learning FPGA Accelerator for Online Fast Adaptation with Selective Mixed-precision Re-trainingWooyoung Jo, Juhyoung Lee, Seunghyun Park, Hoi-Jun Yoo. 1-3 [doi]
- 0.6 V 8.1/0.2µW Ultra-Low-Power Logarithmic Power Detectors Employing Subthreshold MOS TransistorsKeun-Mok Kim, Hyun-Gi Seok, Jeong-Il Seo, Kyung-Sik Choi, Sang-Gug Lee. 1-3 [doi]
- A 4.39ps, 1.5GS/s Time-to-Digital Converter with 4× Phase Interpolation Technique and a 2-D Quantization ArrayYongkuo Ma, Peiyuan Wan, Hongda Zhang, Zhi Wan, Xiaoyu Zhang, Xu Liu, Zhijie Chen. 1-3 [doi]
- An Ultra-Low Close-In Phase Noise Series-Resonance BAW Oscillator in a 130-nm BiCMOS processSachin Kalia, Bichoy Bahr, Tolga Dinc, Baher Haroun, Swaminathan Sankaran. 1-3 [doi]
- A 76-Gbit/s 265-GHz CMOS ReceiverShinsuke Hara, Ruibing Dong, Sangyeop Lee, Kyoya Takano, Naoya Toshida, Satoru Tanoi, Tatsuo Hagino, Mohamed H. Mubarak, Norihiko Sekine, Issei Watanabe, Akifumi Kasamatsu, Kunio Sakakibara, Shunichi Kubo, Satoshi Miura, Yohtaro Umeda, Takeshi Yoshida, Shuhei Amakawa, Minoru Fujishima. 1-3 [doi]
- A 77 MHz Relaxation Oscillator in 5nm FinFET with 3ns TIE over 10K cycles and ±0.3% Thermal Stability using Frequency-Error Feedback LoopNandish Mehta, Stephen G. Tell, Walker J. Turner, Lamar Tatro, Giant Goh, C. Thomas Gray. 1-3 [doi]
- A 2.7W AC-coupled hybrid supply modulator achieving 200MHz envelope-tracking bandwidth for 5G new radio power amplifierPeng Xu, Xueli Zhang, Peng Cao, Tingting Wei, Zhiguo Tong, Jiawei Xu 0001, Zhiliang Hong. 1-3 [doi]
- Realizing Direct Convolution in Memory with Systolic-RAMJacob N. Rohan, Jaydeep P. Kulkarni. 1-3 [doi]
- A 1.68-23.2 Gb/s Reference-Less Half-Rate Receiver with an ISI-Tolerant Unlimited Range Frequency DetectorYu-Ping Huang, Yi-Wei Chang, Wei-Zen Chen. 1-2 [doi]
- A 70mW Indirect Time-of-Flight Image Sensor with Depth Dynamic Range Enhancement and Fixed Depth Noise CompensationCanxing Piao, Yeonsoo Ahn, Donguk Kim, JiHoon Park, Jubin Kang, Minseok Shin, Kangbong Seo, Seong-Jin Kim, Jung-Hoon Chun, Jaehyuk Choi. 1-3 [doi]
- An Output Capacitor-less Low-dropout Regulator using a Wide-range Single-stage Gain-boosted Error Amplifier and a Frequency-dependent Buffer with a Total Compensation Capacitance of 2.5 pF in 0.5 µm CMOSHyeon-Ji Choi, Joo-Mi Cho, Hyo-Jin Park, Sung-Wan Hong. 1-3 [doi]
- A Sort-Less FPGA-Based Non-Maximum Suppression Accelerator using Multi-Thread Computing and Binary Max Engine for Object DetectionChaoming Fang, Habib Derbyshire, Wenyu Sun, Jinshan Yue, Haobing Shi, Yongpan Liu. 1-3 [doi]
- A Millimeter-Scale Computing System with Adaptive Dynamic Load Power TrackingSeokhyeon Jeong, Yejoong Kim, Yuyang Li, Inhee Lee. 1-3 [doi]
- 2 Collision Avoidable RFID Employing Complementary Pass-transistor Adiabatic Logic with an Inductively Connected External AntennaSaito Shibata, Reiji Miura, Yoshiki Sawabe, Kota Shiba, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda. 1-3 [doi]
- A 1.3-Mbit Annealing System Composed of Fully-Synchronized 9-board x 9-chip x 16-kbit Annealing Processor Chips for Large-Scale Combinatorial Optimization ProblemsKasho Yamamoto, Takashi Takemoto, Chihiro Yoshimura, Mayumi Mashimo, Masanao Yamaoka. 1-3 [doi]
- A Multi-phase Series-Parallel with Bond Wire Auxiliary Fully-Integrated 250pF Switched-Capacitor with 13.6mV output ripple for Supplying Temperature Sensor with 0.1°C Accuracy to Early Detect COVID-19Shu-Yung Lin, Chin-Hsiang Liang, Kai-Syun Chang, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai. 1-3 [doi]
- RAODAT: An Energy-Efficient Reconfigurable AI-based Object Detection and Tracking Processor with Online LearningYuchuan Gong, Qingsong Liu, Luying Que, Conghan Jia, Jiahui Huang, Ye Liu, Jiayan Gan, Yuxiang Xie, Yong Zhou, Lili Liu, Xiaoqiang Xiang, Liang Chang 0002, Jun Zhou 0017. 1-3 [doi]
- Zero Current Detector with Slope Judgement Calibration in Mobile Battery Charger ICKye-Seok Yoon, Hye-Bong Ko, Jin-Woo So, Sung-Woo Lee, Sung-Kyu Cho, Woon-Hyung Heo, Ho Sung Son, Seung-Hoon Kim, Dong Joon Kim, Kwon-Yub Hyung, Dae-Woong Cho, Jung-Wook Heo, Hyoung-Seok Oh, Sung-Ung Kwak. 1-3 [doi]
- 2 RF Transceiver in 40nm CMOS for IoT Micro-Hub ApplicationsZexue Liu, Yi Tan, Chen Xu, Heyi Li, Haoyun Jiang, Xinyu Bao, Dong Wang, Junhua Liu, Huailin Liao. 1-3 [doi]
- A 56-Gb/s PAM-4 Optical Transceiver with Nonlinear FFE for VCSEL Driver in 40nm CMOSPen-Jui Peng, Hsiang-En Huang, Wei-Chien Huang, Po-Lin Lee, Ming-Wei Lin, Ying-Zong Juang, Sheng-Hsiang Tseng. 1-3 [doi]
- A 48Gb/s 2.4pJ/b PAM-4 Baud-Rate Digital CDR with Stochastic Phase Detection Technique in 40nm CMOSHaram Ju, KwangHo Lee, Woosong Jung, Deog Kyoon Jeong. 1-3 [doi]
- A 7Gbps (160, 80) Non-Binary LDPC Decoder with Dual-Message EMS Algorithm in 22nm FinFET TechnologyJeongwon Choe, Youngjoo Lee. 1-3 [doi]
- CIM-SECDED: A 40nm 64Kb Compute In-Memory RRAM Macro with ECC Enabling Reliable OperationBrian Crafton, Samuel Spetalnick, Jong-Hyeok Yoon, Wei Wu, Carlos Tokunaga, Vivek De, Arijit Raychowdhury. 1-3 [doi]
- A 24-30GHz 4-Element Phased Array Transceiver with Low Insertion Loss Compact T/R Switch and Bidirectional Phase Shifter in 65 nm CMOS TechnologyXiangrong Huang, Haikun Jia, Shengnan Dong, Wei Deng 0001, Zhihua Wang 0001, Baoyong Chi. 1-3 [doi]
- A ± 20-ppm -50°C-105°C 1-µA 32.768-kHz Clock Generator with a System-HFXO-Assisted Background CalibrationChun-Yu Lin, Yu-Wei Huang, Tsung-Hsien Lin. 1-3 [doi]
- Auto-Calibration Technique for Current-Based Bandgap Voltage ReferenceChi-Wa U, Man Kay Law, Chi-Seng Lam, Rui Paulo Martins. 1-3 [doi]
- Modeling Attack Resistant Strong PUF Exploiting Obfuscated Interconnections With <0.83% Bit-Error RateChongyao Xu, Jieyun Zhang, Man Kay Law, Yang Jiang 0002, Xiaojin Zhao, Pui-In Mak, Rui Paulo Martins. 1-3 [doi]
- An integrated 8A pulsed VCSEL array driver under 12V supply with built-in pulse monitor and automatic peak current control for direct time-of-flight applicationsTao Xia, XueFeng Chen, Yuwei Wang, Yuan Li, Yifan Wu, Lei Wang, Liujia Song, Shenglong Zhuo, Zhihong Lin, Patrick Yin Chiang. 1-3 [doi]
- FPGA-Based Ordered Statistic Decoding Architecture for B5G/6G URLLC IIOT NetworksChanghyeon Kim, Dongyoung Rim, Jeongwon Choe, Dongyun Kam, Giyoon Park, Seokki Kim, Youngjoo Lee. 1-3 [doi]
- A Hybrid ZQ Calibration Design for High-Density Flash Memory Toggle 5.0 High-speed InterfaceTongsung Kim, Anil Kavala, Hyunsuk Kang, Youngmin Jo, Jungjune Park, Kyoungtae Kang, Byung-Kwan Chun, Dong-Ho Shin, Dong-Su Jang, Byunghoon Jeong, Chiweon Yoon, Jinyub Lee, Jai Hyuk Song. 1-2 [doi]
- A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated JitterMario Mercandelli, Luca Bertulessi, Carlo Samori, Salvatore Levantino. 1-3 [doi]
- A 24-to-32GHz series-Doherty PA with two-step impedance inverting power combiner achieving 20.4dBm Psat and 38%/34% PAE at Psat/6dB PBO for 5G applicationsMasoud Pashaeifar, Anil Kumar Kumaran, Mohammadreza Beikmirza, Leo C. N. de Vreede, Morteza S. Alavi. 1-3 [doi]
- A 139 fps pixel-level pipelined binocular stereo vision accelerator with region-optimized semi-global matchingPingcheng Dong, Zhuoao Li, Zhuoyu Chen, Ruoheng Yao, Huanshihong Deng, Wenyue Zhang, Yangyi Zhang, Lei Chen, Chao Wang, Fengwei An. 1-3 [doi]
- A 45.4x∼221.2x latency Improvement of SRP-5 Cryptographic Engine for Smart Grid NetworkYa-Yun Hou, Shaopeng Lai, Hung-Kun Chang, Yun-Wen Lu, Hsie-Chia Chang. 1-3 [doi]
- A Computationally Efficient, Hardware Re-configurable Architecture for QRS Detection and ECG authenticationWeihong Yan, Yuxin Ji, Ce Ma, Lining Hu, Yang Zhao, Yongfu Li, Guoxing Wang, Yong Lian. 1-2 [doi]
- A Cross-Correlation-Based Time-of-Flight Design for Chaos Lidar SystemsYi-Cheng Lin, Ping-Hsuan Hsieh, Jian-Lun Hong, Yu-Hsiang Lai, Jun-Da Chen, Fan-Yi Lin, Yuan-Hao Huang, Po-Chiun Huang. 1-3 [doi]
- A 4.57 μW@120fps Vision System of Sensing with Computing for BNN-Based Perception ApplicationsHan Xu, Zheyu Liu, Ziwei Li, Erxiang Ren, Maimaiti Nazhamati, Fei Qiao, Li Luo, Qi Wei, Xinjun Liu, Huazhong Yang. 1-3 [doi]
- A 1596GB/s 48Gb Embedded DRAM 384-Core SoC with Hybrid Bonding IntegrationXiping Jiang, Fengguo Zuo, Song Wang, Xiaofeng Zhou, Bing Yu, Yubing Wang, Qi Liu, Ming Liu, Yi Kang, Qiwei Ren. 1-3 [doi]
- Correlated Dual-Loop Sturdy MASH CT ΔΣ ADC with Indirect Signal FeedforwardBeomsoo Park, Changsok Han, Nima Maghari. 1-3 [doi]
- 1.55mW 2GHz ERBW 7b 800MS/s 3-stage Pipelined SAR ADC in 28nm CMOS using a Kickback-Cancelling 7T-Dynamic Residue Amplifier with only 16fF Input CapacitanceHyeonsik Kim, Seonkyung Kim, Jintae Kim. 1-3 [doi]
- -17 dBm Differential charge pump EPC Gen2 UHF RFID demodulator for 9 dB receive sensitivity boostAnand Savanth, Philex Ming-Yan Fan, Sahan Gamage, Thanushree Achuthan, Fernando García-Redondo. 1-3 [doi]
- A 196.2 dBc/Hz FOMT 16.8-to-21.6 GHz Class-F23 VCO with Transformer-Based Optimal Q-factor Tank in 65-nm CMOSFeifan Hong, Tianao Ding, Dixian Zhao. 1-3 [doi]
- A 24Gb/s/pin PAM-4 Built Out Tester chip enabling PAM-4 chips test with NRZ interface ATEHyungmin Jin, Jindo Byun, Hyunyoon Cho, Hojun Yoon, Jin-Hee Park, Kyoungsoo Kim, Youngdon Choi, Jung Hwan Choi, Hyungjong Ko, Sang Hyun Lee. 1-3 [doi]
- An Input-buffer Embedding Dual-residue Pipelined-SAR ADC with Nonbinary Capacitive InterpolationSeung-Yong Lim, Raymond Mabilangan, Dong-Jin Chang, Young-Jae Cho, Michael Choi, Seung-Tak Ryu. 1-3 [doi]
- A 7m-range, 4.3mW/Ch. Ultrasound ASIC with Universal Energy Recycling TX for All-Weather Metamorphic Robotic 3D Vision SystemHan Wu, Miaolin Zhang, Jiaqi Guo, Zhichun Shao, Kian Ann Ng, Jiamin Li, Lian Zhang, Yilong Dong, Liuhao Wu, Chne Wuen Tsai, Ho Yin Benjamin Lee, Liwei Lin, Jerald Yoo. 1-3 [doi]
- 2 103dB DR Switched-Capacitor Audio Delta-Sigma Modulator Using Input-Referred kT/C Noise Reduction TechniqueYong-Sik Kwak, Ho-Jin Kim, Kang-Il Cho, Jun-Ho Boo, Gil-Cho Ahn. 1-3 [doi]
- An Arithmetic Progression Switched-Capacitor DC-DC Converter with Soft VCR Transitions Achieving 93.7% Peak Efficiency and 400 mA Output CurrentYang Jiang 0002, Man Kay Law, Pui-In Mak, Rui Paulo Martins. 1-3 [doi]
- A 7.9-14.3GHz -243.3dB FoMT Sub-Sampling PLL with Transformer-Based Dual-Mode VCO in 40nm CMOSYizhuo Wang, Tenghao Zou, Bowen Chen, Shujiang Ji, Chao Zhang, Na Yan. 1-3 [doi]
- A 50.4 GOPs/W FPGA-Based MobileNetV2 Accelerator using the Double-Layer MAC and DSP Efficiency EnhancementJixuan Li, Jiabao Chen, Ka-Fai Un, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins. 1-3 [doi]
- A Hybrid Continuous Time Incremental and SAR Two-Step ADC with 90.5dB DR over 1MHz BWYanchao Wang 0001, Siladitya Dey 0002, Tao He 0001, Lukang Shi, Jiawei Zheng, Manjunath Kareppagoudr, Yi Zhang 0023, Kazuki Sobue, Koichi Hamashita, Koji Tomioka, Gabor C. Temes. 1-3 [doi]
- A Neural Stimulation IC Based on a Reconfigurable Current DAC with In-Situ Neural Recording Function for Cochlear Implant SystemsWoojin Ahn, Doohee Kim, Jonghyeok Park, Jeong Hoan Park, Taeju Lee, Kyeong-Won Jeon, Kyou Sik Min, Hoseung Lee, Minkyu Je. 1-3 [doi]
- A Programmable 6T SRAM-Based PUF with Dynamic Stability Data MaskingLu Lu 0013, Tony Tae-Hyoung Kim. 1-3 [doi]
- A Low Noise and Linearity Improvement CMOS Image Sensor for Surveillance Camera with Skew-Relaxation Local Multiply Circuit and On-Chip Testable Ramp GeneratorWataru Saito, Yoichi Iizuka, Norihito Kato, Ryota Otake, Fukashi Morishita. 1-3 [doi]
- A Single-Channel 1.75GS/s, 6-Bit Flash-Assisted SAR ADC with Self-Adaptive Timer and On-Chip Offset CalibrationYu-Sian Liao, Wei-Zen Chen. 1-3 [doi]
- An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator without Accuracy Loss in 28nm CMOSZiyu Li, Weiwei Shan, Chengjun Wu, Haitao Ge, Jun Yang 0006. 1-3 [doi]
- A 10 GHz Dual-Loop PLL with Active Noise Cancellation Achieving 12dB Spur and 29% Noise ReductionYu-Sian Lu, Cheng-Lung Lee, Wei-Zen Chen. 1-2 [doi]
- A 1.18mW Double Ratchet Cryptographic Processor with Backward Secrecy for IoT DevicesSheng-Jung Yu, Yu-Chi Lee, Chia-Hsiang Yang. 1-3 [doi]
- FlashMAC: An Energy-Efficient Analog-Digital Hybrid MAC with Variable Latency-Aware SchedulingSurin Gweon, Sanghoon Kang, Donghyeon Han, Kyoung-Rog Lee, Kwantae Kim, Hoi-Jun Yoo. 1-3 [doi]
- An 8.7 μJ/class. FFT accelerator and DNN-based configurable SoC for Multi-Class Chronic Neurological Disorder DetectionZain Taufique, Bingzhao Zhu, Gianluca Coppola, Mahsa Shoaran, Wala Saadeh, Muhammad Awais Bin Altaf. 1-3 [doi]
- A 3.1-μW BJT-Based CMOS Temperature-to-Frequency Converter with Untrimmed Inaccuracy of ±1°C (3σ) from -40°C to 140°CJee Ho Park, Jung-Hye Hwang, Changyong Shin, Seong-Jin Kim. 1-3 [doi]
- A 1.92GHz-3.84GHz 0.74ps-1.09ps-Jitter Inductor-less Injection-Locked Frequency Synthesizer with Automatic Frequency Selection and Timing AlignmentKhoi T. Phan, Yue Chao, Howard C. Luong. 1-3 [doi]
- A 48 Gb/s PAM4 receiver with Baud-rate phase-detector for multi-level signal modulation in 40 nm CMOSKwangHo Lee, Woosong Jung, Haram Ju, Jinhyung Lee, Deog Kyoon Jeong. 1-3 [doi]
- A 2.7-Gb/s Multiplexed-DLL-Based CDR Circuit for ±10% Clock-Embedded Spread-Spectrum Modulation DepthYen-Kuei Lu, Miao-Shan Li, Ching-Yuan Yang, Chin-Lung Lin. 1-3 [doi]
- A 21Gb/s Duobinary Transceiver for GDDR interfaces with an Adaptive EqualizerJae-Woo Park, Dongsuk Kang, Injae Park, Minsu Park, Xuefan Jin, Kyu-Dong Hwang, Dae-Han Kwon, Jung-Hoon Chun. 1-3 [doi]
- A current-integrated differential NAND-structured PUF for stable and V/T variation-tolerant low-cost IoT securityJongmin Lee, Yoonmyung Lee. 1-3 [doi]
- A Feedback Architecture of High Speed True Random Number Generator based on Ring OscillatorXin Cheng, Haowen Zhu, Xinyi Xing, Yunfeng Zhang, Yongqiang Zhang 0006, Guangjun Xie, Zhang Zhang. 1-3 [doi]
- A 4.2mW 4K 6-8GHz CMOS LNA for Superconducting Qubit ReadoutAlican Çaglar, Steven Van Winckel, Steven Brebels, Piet Wambacq, Jan Craninckx. 1-3 [doi]
- A 28.8mW Accelerator IC for Dark Channel Prior Based Blind Image DeblurringPo-Shao Chen, Yen-Lung Chen, Yu-Chi Lee, Fu Zih-Sing, Chia-Hsiang Yang. 1-3 [doi]
- A process scalable voltage-reference-free temperature sensor utilizing MOSFET threshold voltage variationShogo Harada, Mahfuzul Islam, Takashi Hisakado, Osami Wada. 1-3 [doi]
- A Two-Tone Wake-Up Receiver with an Envelope-Detector-First Architecture Using Envelope Biasing and Active Inductor Load Achieving 41/33dB In-Band Rejection to CW/AM InterferenceDawei Ye, Yuting Tu, Wenjun Gong, Rongjin Xu, C.-J. Richard Shi. 1-3 [doi]
- A 95% Peak Efficiency Modified KY (Boost) Converter for IoT with Continuous Flying Capacitor Charging in DCMWen-Liang Zeng, Caolei Pan, Chi-Seng Lam, Sai-Weng Sin, Chenchang Zhan, Rui Paulo Martins. 1-3 [doi]
- A 150-to-1050 GHz Terahertz Detector in 65 nm CMOSZhao-yang Liu, Feng Qi, Yelong Wang, Pengxiang Liu, Wei-fan Li. 1-3 [doi]
- A 64 Gb/s 2.09 pJ/b PAM-4 VCSEL Transmitter with Bandwidth Extension Techniques in 40 nm CMOSHyungrok Do, Jung-Woo Sull, Seunghyun Lee, KwangHo Lee, Deog Kyoon Jeong. 1-3 [doi]
- A 87.2%-Efficiency 27.12MHz Current-Mode Wireless Power Receiver with Ramp-Assisted Energy Delivery Controller for Implantable DevicesZiyang Luo, Hoi Lee. 1-3 [doi]
- A 28.2 μC Neuromorphic Sensing System Featuring SNN-based Near-sensor Computation and Event-Driven Body-Channel Communication for Insertable Cardiac MonitoringYuming He, Federico Corradi, Chengyao Shi, Ming Ding 0003, Martijn Timmermans, Jan Stuijt, Pieter Harpe, Ilja Ocket, Yao-Hong Liu. 1-3 [doi]
- A 640×512 30μm Pixel Pitch 1.8mK-NETD 90.1dB-SNR Digital Read-out Integrated Circuit with Fully On-chip Image Algorithm Pixel-Level CalibrationYan Zeng, Shiheng Yang, Yueduo Liu, Zehao Li, Wengang Huang, Xiaozong Huang, Xiong Zhou, Jiaxin Liu, Qiang Li 0021. 1-3 [doi]
- A 12-ENOB Second-Order Noise Shaping SAR ADC with PVT-insensitive Voltage-Time-Voltage ConverterChih-Cheng Chen, Chih-Cheng Hsieh. 1-3 [doi]
- nd-Harmonic Resonance Achieving 187-to-188.1dBc/Hz FoM in 28nm CMOSXi Meng, Junqi Guo, Haoran Li, Jun Yin 0001, Pui-In Mak, Rui Paulo Martins. 1-3 [doi]
- Dynamic Voltage Stress Sensing Circuits for Screening Out Early Device Reliability Issues in Advanced Technology NodesGhil-Geun Oh, Min-Hye Ho, Yeon-Jung Shin, Jaewook Choi, Ju-Youn Kim, Young Dae Kim. 1-3 [doi]
- 2 21.5-aF Resolution Continuous-Time Delta-Sigma Capacitance-to-Digital Converter with Parasitic Capacitance Immunity up to 480pFHyeyeon Lee, Changuk Lee, Jae-Youl Lee, Yoon Kyung Choi, Youngcheol Chae. 1-3 [doi]
- A 3-to-78GHz Differential Distributed Amplifier with Ultra- Balanced Active Balun and Gain Boosting Techniques in 65-nm CMOS ProcessJinCheng Zhang, Tianxiang Wu, Yong Chen 0005, Junyan Ren, Shunli Ma. 1-3 [doi]
- A 0.79-1.16-GHz Synthesizable Fractional-N PLL Using DTC-Based Multi-Stage Injection with Dithering-Assisted Local Skew Calibration Achieving -232.8-dB FoMrefZule Xu. 1-3 [doi]
- Tiny neural network search and implementation for embedded FPGA: a software-hardware co-design approachJinyu Bai, Yunqian Fan, Sifan Sun, Wang Kang, Weisheng Zhao. 1-3 [doi]
- A 389TOPS/W, 1262fps at 1Meps Region Proposal Integrated Circuit for Neuromorphic Vision Sensors in 65nm CMOSSumon Kumar Bose, Arindam Basu. 1-3 [doi]
- A 99.5dB-DR 5kHz-BW Closed-Loop Neural-Recording IC based on Continuous-Time Dynamic-Zoom ΔΣ ADC with Automatic AFE-Gain ControlYoontae Jung, Soon-Jae Kweon, Hyuntak Jeon, Taeju Lee, Injun Choi, Kyeongwon Jeong, Mi Kyung Kim, Hyunjoo Jenny Lee, Sohmyung Ha, Minkyu Je. 1-3 [doi]
- A 1448-Mpixel/s, 84-pJ/Pixel Display Stream Compression Encoder in 28 nm for 4K Video ResolutionShifu Wu, K. De Silva, Snehlata Gutgutia, Bevan M. Baas, Massimo Alioto. 1-3 [doi]
- A 5.7GHz RF Wireless Power Transfer Receiver Using 84.5% Efficiency 12V SIDO Buck-Boost DC-DC Converter with Internal Power Supply ModeTomohiro Higuchi, Dai Suzuki, Ryo Ishida, Yasuaki Isshiki, Kazuki Arai, Kohei Onizuka, Kousuke Miyaji. 1-3 [doi]
- Self-powered light sensor for simultaneous intensity-and-direction sensing and maximum-energy harvesting with shared photodiodesTai-Haur Kuo, Kuan-Yu Chen, Hsiao-Ping Lin, Shang-Jung Liu. 1-3 [doi]
- An Adaptive Clocking System using Supply Tracking Clock Modulator with Background Calibrated Supply-Sensitivity in 28nm CMOSDongin Kim, SeongHwan Cho. 1-3 [doi]
- A 4th-order CT I-DSM with Digital Noise Coupling and Input Pre-conversion Method for InitializationYe-Dam Kim, Jae-Hyun Chung, Kent Edrian Lozada, Dong-Jin Chang, Seung-Tak Ryu. 1-3 [doi]
- Energy Efficient Design Through Design and Technology Co-Optimization Near the Finish Line of CMOS ScalingShenggao Li, Chien-Chun Tsai, Eric Soenen, Frank J. C. Lee, Cheng-Hsiang Hsieh. 1-3 [doi]
- A 16Kb Transpose 6T SRAM In-Memory-Computing Macro based on Robust Charge-Domain ComputingJiahao Song, Yuan Wang 0001, Xiyuan Tang, Runsheng Wang, Ru Huang. 1-3 [doi]
- A Wirelessly-Powered 10Mbps 46-pJ/b Body Channel Communication System with 45% PCE Multi-Stage and Multi-Source Rectifier for Neural Interface ApplicationsByeongseol Kim, Beomjin Yuk, Joonsung Bae. 1-3 [doi]
- A Reconfigurable Matrix Multiplication Coprocessor with High Area and Energy Efficiency for Visual Intelligent and Autonomous Mobile RobotsJipeng Wang, Yi Zhan, Zhaoxu Wang, Zixuan Peng, Jiarui Xu, Bingqiang Liu, Guoyi Yu, Fengwei An, Chao Wang, Xuecheng Zou. 1-3 [doi]