Energy Efficient Design Through Design and Technology Co-Optimization Near the Finish Line of CMOS Scaling

Shenggao Li, Chien-Chun Tsai, Eric Soenen, Frank J. C. Lee, Cheng-Hsiang Hsieh. Energy Efficient Design Through Design and Technology Co-Optimization Near the Finish Line of CMOS Scaling. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2021, Busan, Korea, Republic of, November 7-10, 2021. pages 1-3, IEEE, 2021. [doi]

Abstract

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