Table of Contents

• An 85dB dynamic range transimpedance amplifier in 40nm CMOS technologyMohammed Hassan, Horst Zimmermann. 1-4 [doi]
• Modeling of cascode modulated power amplifiersDaniel Sira, Torben Larsen. 1-4 [doi]
• Electrical properties of CVD-graphene FETsJohanna Anteroinen, Wonjae Kim, Kari Stadius, Juha Riikonen, Harri Lipsanen, Jussi Ryynänen. 1-4 [doi]
• A 0.13µm CMOS ΔΣ PLL FM transmitterYing Wu, Xiaodong Liu, Dawei Ye, Vijay Viswam, Lin Zhu, Ping Lu, Dejan Radjen, Henrik Sjöland. 1-4 [doi]
• Initial version of Matlab/Simulink based tool for VHDL code generation and FPGA implementation of Elementary Generalized Unitary rotationGatis Valters. 1-6 [doi]
• A divide-by-three regenerative frequency divider using a subharmonic mixerBrad R. Jackson, Carlos E. Saavedra. 1-4 [doi]
• A digital PLL with a multi-delay coarse-fine TDCYing Wu, Ping Lu, Pietro Andreani. 1-4 [doi]
• Single-ended low noise multiband LNA with programmable integrated matching and high isolation switchesTobias Tired, Pietro Andreani. 1-4 [doi]
• A GALS ASIC implementation from a CAL dataflow descriptionHemanth Prabhu, Sherine Thomas, Joachim Neves Rodrigues, Thomas Olsson, Anders Carlsson. 1-4 [doi]
• Comparison and IIP2 analysis of two wideband Balun-LNAs designed in 65nm CMOSLin Zhu, Martin Liliebladh. 1-4 [doi]
• Dynamic bias schemes for class-C VCOsLuca Fanori, Pietro Andreani. 1-4 [doi]
• Yield modeling and yield-aware mapping for application specific networks-on-chipSeyyed Hassan Khalilinezhad, Akram Reza, Midia Reshadi. 1-4 [doi]
• A low-cost processing element recovery mechanism for fault tolerant Networks-on-ChipKhalid Latif 0002, Amir-Mohammad Rahmani, Tiberiu Seceleanu, Hannu Tenhunen. 1-4 [doi]
• Model-based rapid prototyping of multirate digital signal processing algorithmsShahzad Ahmad Butt, Luciano Lavagno. 1-4 [doi]
• FPGA implementation of decimal processors for hardware accelerationNicolas Borup, Jonas Dindorp, Alberto Nannarelli. 1-4 [doi]
• Adaptive photovoltaic cell simulation with maximum power point tracking simulation for accurate energy predictionsChristian Schuss, Timo Rahkonen. 1-4 [doi]
• A mixed mode design flow for multi GHz ADPLLsMuhammad Shakir, Mohammed Abdulaziz, Ping Lu, Pietro Andreani. 1-4 [doi]
• Contention aware scheduling for NoC-based real-time systemsMihkel Tagel, Peeter Ellervee, Thomas Hollstein, Gert Jervan. 1-4 [doi]
• A novel low-energy match line sensing scheme for ternary content addressable memory using charge sharingSyed Iftekhar Ali, M. S. Islam. 1-4 [doi]
• Very high bandwidth semi-digital PLL with large operating frequency rangeVivek Elangovan, Markus Dietl, Puneet Sareen. 1-6 [doi]
• Charge scaling 10-bit successive approximation A/D converter with reduced input capacitanceOlli Kursu, Timo Rahkonen. 1-4 [doi]
• On hardware implementation of radix 3 and radix 5 FFT kernels for LTE systemsJohan Löfgren, Peter Nilsson. 1-4 [doi]
• Temperature dependent wire delay estimation in floorplanningAndreas Thor Winther, Wei Liu, Alberto Nannarelli, Sarma B. K. Vrudhula. 1-4 [doi]
• Magnitude scaling for increased SFDR in DDFSPetter Kallstrom, Oscar Gustafsson. 1-4 [doi]
• A fault-tolerant and hierarchical routing algorithm for NoC architecturesMojtaba Valinataj, Pasi Liljeberg, Juha Plosila. 1-6 [doi]
• Low power programmable frequency divider for IEEE 802.15.4a standardDenys I. Martynenko, Gunter Fischer, Oleksiy Klymenko. 1-4 [doi]
• Computational and implementation complexity of polynomial evaluation schemesMuhammad Abbas, Oscar Gustafsson. 1-6 [doi]
• An adaptive router architecture for heterogeneous 3D Networks-on-ChipMichael Opoku Agyeman, Ali Ahmadinia. 1-4 [doi]
• Impact of switching activity on the energy minimum voltage for 65 nm sub-VT CMOSOskar Andersson, S. M. Yasser Sherazi, Joachim Neves Rodrigues. 1-4 [doi]
• Implementation of narrow-band frequency-response masking for efficient narrow transition band FIR filters on FPGAsSyed Asad Alam, Oscar Gustafsson. 1-4 [doi]
• Wideband limit study of a GaN power amplifier using two-tone measurementsFelice Francesco Tafuri, Daniel Sira, Troels Studsgaard Nielsen, Ole Kiel Jensen, Torben Larsen. 1-4 [doi]
• Comparison of time-varying and non-time-varying Volterra analysis for finding distortion contributions in mixersTimo Rahkonen, Janne Aikio, Juha-Pekka Hamina. 1-4 [doi]
• Injection-locked superharmonic self-oscillating mixerTero Koivisto, Esa Tiiliharju, Peter Virta. 1-4 [doi]
• Explorations of optimal core and cache placements for Chip MultiprocessorThomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen. 1-6 [doi]
• A 2.7-6.1GHz CMOS local oscillator based on frequency multiplication by 3/2Andrea Bevilacqua, Pietro Andreani. 1-4 [doi]
• On wafer X-parameter based modeling of a switching cascode power amplifierYelin Wang, Daniel Sira, Troels Studsgaard Nielsen, Ole K. Jensen, Torben Larsen. 1-4 [doi]
• Square topology: A novel topology for NoCsHossein Doroud, Mahsa Ghorbanian, Reza Sabbaghi-Nadooshan. 1-4 [doi]
• A continuous time ΔΣ modulator with reduced clock jitter sensitivity through DSCR feedbackDejan Radjen, Pietro Andreani, Martin Anderson, Lars Sundström. 1-4 [doi]
• A linearized 1.6-5 GHz low noise amplifier using positive feedback in 65 nm CMOSAnders Nejdel, Markus Törmänen, Henrik Sjöland. 1-4 [doi]
• Highly linear direct conversion receiver using customized on-chip balunXiaodong Liu, Vijay Viswam, Stefan Back Andersson, Johan Wernehag, Imad ud Din, Pietro Andreani. 1-4 [doi]
• 10 GS/s 8-bit bipolar THA in SiGe technologyYevgen Borokhovych, Christoph Scheytt. 1-4 [doi]
• IR-UWB technology on next generation RFID systemsKin Keung Lee, Håkon A. Hjortland, Tor Sverre Lande. 1-4 [doi]
• Transistor sizing for a 4-state current mode analog channel decoder in 65-nm CMOSReza Meraji, John B. Anderson, Henrik Sjöland, Viktor Öwall. 1-4 [doi]
• A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOSMohammed Abdulaziz, Muhammad Shakir, Ping Lu, Pietro Andreani. 1-4 [doi]
• Architecture-level analysis and evaluation of transient errors on NoCJiajia Jiao, Yuzhuo Fu, Jiang Jiang. 1-4 [doi]
• Highly reliable and power efficient NOC interconnectsDeena M. Zamzam, Mohamed A. Abd El ghany, Klaus Hofmann, Mohammad Ismail. 1-4 [doi]
• A Ternary Adiabatic Logic (TAL) implementation of a four-trit Full-AdderDavid J. Willingham, Izzet Kale. 1-4 [doi]
• Measurement of a system-adaptive error-detection sequential circuit with subthreshold SCLMatthew J. Turnquist, Erkka Laulainen, Jani Mäkipää, Lauri Koskinen. 1-4 [doi]
• A low voltage low power CMOS analog multiplierAmir H. Miremadi, Ahmad Ayatollahi, Adib Abrishamifar. 1-4 [doi]
• An empirical study of the stability of 4th-order Incremental-ΣΔ-ADCsJohannes Uhlig, René Schüffny. 1-4 [doi]
• Use of a calibrated voltage reference to enhance the performance of switched capacitor sigma-delta ADCs over process cornerRonald Spilka, Dominik Gruber, Timm Ostermann. 1-6 [doi]
• Complexity analysis of IOTA filter architectures in faster-than-Nyquist multicarrier systemsDeepak Dasalukunte, Shahid Mehmood, Viktor Öwall. 1-4 [doi]