Myeong-Jae Park, Ho Sung Cho, Tae Sik Yun, Sangjin Byeon, Young Jun Koo, Sang-Sic Yoon, Dong Uk Lee, Seokwoo Choi, Ji-Hwan Park, Jinhyung Lee, Kyungjun Cho, Junil Moon, Byung Kuk Yoon, Young-Jun Park, Sangmuk Oh, Chang Kwon Lee, Tae-Kyun Kim, Seong-Hee Lee, Hyun Woo Kim, Yucheon Ju, Seung-Kyun Lim, Seung Geun Baek, Kyo Yun Lee, Sang-Hun Lee, Woo Sung We, Seungchan Kim, Yongseok Choi, Seong-Hak Lee, Seung-Min Yang, Gunho Lee, In-Keun Kim, Younghyun Jeon, Jae Hyung Park, Jong-Chan Yun, Chanhee Park, Sun-Yeol Kim, Sungjin Kim, Dong Yeol Lee, Su-Hyun Oh, Taejin Hwang, Junghyun Shin, Yunho Lee, Hyunsik Kim, Jaeseung Lee, Youngdo Hur, Sangkwon Lee, Jieun Jang, Junhyun Chun, Joohwan Cho. A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization. In IEEE International Solid-State Circuits Conference, ISSCC 2022, San Francisco, CA, USA, February 20-26, 2022. pages 444-446, IEEE, 2022. [doi]
Abstract is missing.