Harijot Singh Bindra - researchr alias

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Viewing Publication 1 - 14 from 14

2025

2023

A 14-Bit Oversampled SAR ADC With Mismatch Error Shaping and Analog Range CompensationYuting Shen, Hanyue Li, Harijot Singh Bindra, Eugenio Cantatore, Pieter Harpe. tcasII, 70(5):1719-1723, May 2023. [doi]

2022

A 174μVRMS Input Noise, 1 G8/s Comparator in 22nm FDSOI with a Dynamic-Bias Preamplifier Using Tail Charge Pump and Capacitive Neutralization Across the LatchHarijot Singh Bindra, Jeroen Ponte, Bram Nauta. isscc 2022: 1-3 [doi]

Reconstructing Aliased Frequency Spectra by Using Multiple Sample RatesMaikel Huiskamp, Mark S. Oude Alink, Bram Nauta, Anne-Johan Annema, Harijot Singh Bindra. tcasI, 69(3):999-1012, 2022. [doi]

2021

Energy Efficient Startup of Crystal Oscillators Using Stepwise ChargingJoeri Lechevallier, Harijot Singh Bindra, Ronan A. R. van der Zee, Bram Nauta. jssc, 56(8):2427-2437, 2021. [doi]

2019

A 0.2 - 8 MS/s 10b flexible SAR ADC achieving 0.35 - 2.5 fJ/conv-step and using self-quenched dynamic bias comparatorHarijot Singh Bindra, Anne-Johan Annema, Simon M. Louwsma, Bram Nauta. vlsic 2019: 74 [doi]

A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supplyHarijot Singh Bindra, Anne-Johan Annema, Gerard Wienk, Bram Nauta, Simon M. Louwsma. cicc 2019: 1-4 [doi]

2018

A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input NoiseHarijot Singh Bindra, Chris E. Lokin, Daniël Schinkel, Anne-Johan Annema, Bram Nauta. jssc, 53(7):1902-1912, 2018. [doi]

2017

2013

Clock and data recovery module in 90nm for 10Gbps serial link with -18dB channel attenuationHarijot Singh Bindra, Shouri Chatterjee, Kaushik Saha, Taranjit Kukal. iscas 2013: 2472-2475 [doi]

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