Abstract is missing.
- A programmable RFSoC in 16nm FinFET technology for wideband communicationsBrendan Farley, Christophe Erdmann, Bruno Vaz, John McGrath, Edward Cullen, Bob Verbruggen, Roberto Pelliconi, Daire Breathnach, Peng Lim, Ali Boumaalif, Patrick Lynch, Conrado Mesadri, David Melinn, Kwee Peng Yap, Liam Madden. 1-4 [doi]
- A reconfigurable analog baseband transformer for multistandard applications in 14nm FinFET CMOSJongmi Lee, Jongwoo Lee, Chilun Lo, Jaehoon Lee, In-Young Lee, Byungki Han, Seunghyun Oh, Thomas Cho. 5-8 [doi]
- 2 bit cell, 2.7mA/100MHz low-power read and hybrid write verify for high endurance applicationChia-Fu Lee, Hon-Jarn Lin, Chiu-Wang Lien, Yu-Der Chih, Tsung-Yung Jonathan Chang. 9-12 [doi]
- A dynamic power reduction in synchronous 2RW 8T dual-port SRAM by adjusting wordline pulse timing with same/different row access modeYoshisato Yokoyama, Yuichiro Ishii, Haruyuki Okuda, Koji Nii. 13-16 [doi]
- 14nm Broadwell Xeon® processor family: Design methodologies and optimizationsMahesh K. Kumashikar, Shridhar G. Bendi, Srikanth Nimmagadda, Anup Jyoti Deka, Anil Agarwal. 17-20 [doi]
- A dual-axis MEMS vibratory gyroscope ASIC with 0.0061°/s/VHz noise floor over 480 Hz bandwidthZhichao Tan, Khiem Nguyen, Jeff Yan, Howard Samuels, Shane Keating, Paul Crocker, Bill Clark. 21-24 [doi]
- Chaos, deterministic non-periodic flow, for chip-package-board interactive PUFNoriyuki Miura, Masanori Takahashi, Kazuki Nagatomo, Makoto Nagata. 25-28 [doi]
- A 93μW 11Mbps wireless vital signs monitoring SoC with 3-lead ECG, bio-impedance, and body temperatureYuxuan Luo, Kok-Hin Teng, Yongfu Li, Wei Mao, Chun-Huat Heng, Yong Lian. 29-32 [doi]
- A 16-channel TDM analog front-end with enhanced system CMRR for wearable dry EEG recordingTao Tang, Wang Ling Goh, Lei Yao, Yuan Gao. 33-36 [doi]
- An area-efficient amplifier-less digitally-controlled li-ion battery charger in 0.35μm CMOSSheng-Ying Lin, Tsung-Hsien Lin. 37-40 [doi]
- A 0.5V BJT-based CMOS thermal sensor in 10-nm FinFET technologyDa-Shin Lin, Hao-Ping Hong. 41-44 [doi]
- An ultra-low power 169-nA 32.768-kHz fractional-N PLLChun-Yu Lin, Tun-Ju Wang, Tzu-Hsuan Liu, Tsung-Hsien Lin. 45-48 [doi]
- A 10kHz-BW 93.7dB-SNR chopped ΔΣ ADC with 30V input CM range and 115dB CMRR at 10kHzLong Xu, Johan H. Huijsing, Kofi A. A. Makinwa. 49-52 [doi]
- An energy-efficient self-charged crystal oscillator with a quadrature-phase shifter techniqueWei-Sung Chang, Dai-En Jhou, Yu-Hong Yang, Tai-Cheng Lee. 53-56 [doi]
- An area-efficient capacitively-coupled sensor readout circuit with current-splitting OTA and FIR-DACChih-Chan Tu, Feng-Wen Lee, Han-Chun Chen, Yu-Kai Wang, Tsung-Hsien Lin. 57-60 [doi]
- 25 fJ/bit, 5Mb/s, 0.3 V true random number generator with capacitively-coupled chaos system and dual-edge sampling schemeAnh-Tuan Do, Xin Liu. 61-64 [doi]
- 2 AES core with DPA resistance for IoT devicesShengshuo Lu, Zhengya Zhang, Marios C. Papaefthymiou. 65-68 [doi]
- 2 voltage scalable digital frequency generator for SoC clockingMartin Cochet, Sylvain Clerc, Guenole Lallement, Fady Abouzeid, Philippe Roche, Jean-Luc Autran. 69-72 [doi]
- A 10-GHz multi-purpose reconfigurable built-in self-test circuit for high-speed linksMyungguk Lee, Seungho Han, Jae-Yoon Sim, Hong June Park, Byungsub Kim. 73-76 [doi]
- A 56Gbps PAM-4 optical receiver front-endKuan-Lin Fu, Shen-Iuan Liu. 77-80 [doi]
- A low-power PAM4 receiver using 1/4-rate sampling decoder with adaptive variable-gain rectificationGuang Zhu, Quan Pan, John Zhuang, Charlie Zhi, C. Patrick Yue. 81-84 [doi]
- A 82 mW 28 Gb/s PAM-4 digital sequence decoder with built-in error correction in 28nm FDSOIMasum Hossain, Aurangozeb, A. K. M. Delwar Hossain, Maruf Mohammad. 85-88 [doi]
- A 51Gb/s, 320mW, PAM4 CDR with baud-rate sampling for high-speed optical interconnectsNan Qi, Yuhang Kang, Qipeng Lin, Jianxu Ma, Jingbo Shi, Bozhi Yin, Chang Liu, Rui Bai, Shang Hu, Juncheng Wang, Jiangbing Du, Lin Ma, Zuyuan He, Ming Liu, Feng Zhang, Patrick Yin Chiang. 89-92 [doi]
- A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOSPeng Chen, Feifei Zhang, Zhirui Zong, Hao Zheng, Teerachot Siriburanon, Robert Bogdan Staszewski. 93-96 [doi]
- A 173-200 GHz quadrature voltage-controlled oscillator in 130 nm SiGe BiCMOSPaul Stärke, Vincent Ries, Corrado Carta, Frank Ellinger. 97-100 [doi]
- A 67 GHz dual injection quadrature VCO with -182.9 dBc/Hz FOM in 90-nm CMOSCuei-Ling Hsieh, Hong-Shen Chen, Hou-Ru Pan, Jenny Yi-Chun Liu. 101-104 [doi]
- A 350-mV 2.4-GHz quadrature oscillator with nearly instantaneous start-up using series LC tanksYue Chen, Masoud Babaie, Robert Bogdan Staszewski. 104-108 [doi]
- On-chip spur and phase noise cancellation techniquesYi-An Li, Monte Mar, Borivoje Nikolic, Ali M. Niknejad. 109-112 [doi]
- A single-inductor triple-input-triple-output (SITITO) energy harvesting interface with cycle-by-cycle source tracking and adaptive peak-inductor-current controlChi-Wei Liu, Ming-Jie Chung, Hui-Hsuan Lee, Pei-Chun Liao, Po-Hung Chen. 113-116 [doi]
- An 88% efficiency MPPT for PV energy harvesting system with novel switch width modulation for output power 100nW to 0.3mWKarim Rawy, Taegeun Yoo, Tony T. Kim. 117-120 [doi]
- A DVS-based burst mode with automatic entrance point control technique in DC-DC boost converter for wearable devices and IoT applicationsChiao-Hung Cheng, Li-Chi Lin, Jian-He Lin, Ke-Horng Chen, Ying-Hsi Lin, Jian-Ru Lin, Tsung-Yen Tsai. 121-124 [doi]
- A wide load and voltage range switched-capacitor DC-DC converter with load-dependent configurability for DVS implementation in miniature sensorsHassan Saif, Yongmin Lee, Minsun Kim, Hyeonji Lee, Muhammad Bilawal Khan, Yoonmyung Lee. 125-128 [doi]
- A high efficiency and fast transient digital low-dropout assisted switched-capacitor converter for EMI-free Internet of Everything (IoE) systemsShao-Qi Chen, Yen-Ting Lin, Yu-Sheng Ma, Wen-Hau Yang, Ke-Horng Chen, Ying-Hsi Lin, Jian-Ru Lin, Tsung-Yen Tsai. 129-132 [doi]
- A CMOS time of flight (TOF) depth image sensor with in-pixel background cancellation and sensitivity improvement using phase shifting readout techniqueTing Liao, Nien-An Lee, Chih-Cheng Hsieh. 133-136 [doi]
- An element-matched band-pass delta-sigma ADC for ultrasound imagingMichele D'Urbino, Chao Chen, Zhao Chen, Zu-yao Chang, Jacco Ponte, nBoris Lippe, Michiel Pertijs. 137-140 [doi]
- A 12.1mW, 60dB SNR, 8-channel beamforming embedded SAR ADC for ultrasound imaging systemsTaehoon Kim, Suhwan Kim. 141-144 [doi]
- A 2.79-mW 0.5%-THD CMOS current driver IC for portable electrical impedance tomography systemJaeeun Jang, Minseo Kim, Joonsung Bae, Hoi-Jun Yoo. 145-148 [doi]
- 0.5 and 1.5 THz monolithic imagers in a 65 nm CMOS adopting a VCO-based signal processingSun-a Kim, Kyoung-Yong Choi, Dae-Woong Park, Joo-Myoung Kim, Seok-Kyun Han, Sang-Gug Lee. 149-152 [doi]
- Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAMChang-Kyo Lee, Junha Lee, Kiho Kim, Jin-Seok Heo, Gil-Hoon Cha, Jin-Hyeok Baek, Daesik Moon, Yoon-Joo Eom, Tae Sung Kim, Hyunyoon Cho, Young Hoon Son, Seonghwan Kim, Jong-Wook Park, Sewon Eom, Si-Hyeong Cho, Young-Ryeol Choi, SeungSeob Lee, Kyoung-Soo Ha, Youngseok Kim, Bo-Tak Lim, Dae-Hee Jung, Eungsung Seo, Kyoung-Ho Kim, Yoon-Gyu Song, Youn-Sik Park, Tae-young Oh, Seung-Jun Bae, Indal Song, Seok-Hun Hyun, Joon Young Park, Hyuck-Joon Kwon, Young-Soo Sohn, Jung Hwan Choi, Kwang-Il Park, Seong-Jin Jang. 153-156 [doi]
- MLC/3LC NAND flash SSD cache with asymmetric error reduction huffman coding for tiered hierarchical storageHikaru Watanabe, Yoshiaki Deguchi, Ken Takeuchi. 157-160 [doi]
- Word-line batch Vth modulation of TLC NAND flash memories for both write-hot and cold dataYoshiaki Deguchi, Ken Takeuchi. 161-164 [doi]
- A 16kb column-based split cell-VSS, data-aware write-assisted 9T ultra-low voltage SRAM with enhanced read sensing margin in 28nm FDSOIM. Sultan M. Siddiqui, Zhao Chuan Lee, Tony Tae-Hyoung Kim. 165-168 [doi]
- An energy-optimized (37840, 34320) symmetric BC-BCH decoder for healthy mobile storagesSeokha Hwang, Jaehwan Jung, Daesung Kim, Jeongseok Ha, In-Cheol Park, Youngjoo Lee. 169-172 [doi]
- A 130nm 1Mb HfOx embedded RRAM macro using self-adaptive peripheral circuit system techniques for 1.6X work temperature rangeFeng Zhang, Dongyu Fan, Yuan Duan, Jin Li, Cong Fang, Yun Li, Xiaowei Han, Lan Dai, Cheng-Ying Chen, Jinshun Bi, Ming Liu, Meng-Fan Chang. 173-176 [doi]
- A reconfigurable dual-band WiFi/BT combo transceiver with integrated 2G/BT SP3T, LNA/PA achieving concurrent receiving and wide dynamic range transmitting in 40nm CMOSMeng-Hsiung Hung, Yi-Shing Shih, Chin-Fu Li, Wei-Kai Hong, Ming-Yeh Hsu, Chih-Hao Chen, Yu-Lun Chen, Chun-Wei Lin, Yuan-Hung Chung. 177-180 [doi]
- A high-speed DDFS MMIC with frequency, phase and amplitude modulations in 65nm CMOSAbdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa. 181-184 [doi]
- A -121dBm sensitivity, 2μJ/bit Rx, 8.8μJ/bit Tx, narrowband transceiver for ARIB STD and IoTM. Kumarasamy Raja, Zhao Bin, Dan Lei Yan, Hongbao Zhang, Wei Yi Lim, John Leo Chemmanda. 185-188 [doi]
- Detection of 3.0 THz wave with a detector in 65 nm standard CMOS processTong Fang, Zhao-yang Liu, Liyuan Liu, Yuan-Yuan Li, Jun-qi Liu, Jian Liu, Nanjian Wu. 189-192 [doi]
- A 0.6-V 200-kbps 429-MHz ultra-low-power FSK transceiver in 90-nm CMOSChun-Yuan Chiu, Zhen-Cheng Zhang, Tsung-Hsien Lin. 193-196 [doi]
- An 82% energy-saving change-sensing flip-flop in 40nm CMOS for ultra-low power applicationsVan Loi Le, Juhui Li, Alan Chang, Tony T. Kim. 197-200 [doi]
- NBTI/PBTI separated BTI monitor with 4.2x sensitivity by standard cell based unbalanced ring oscillatorMitsuhiko Igarashi, Yoshio Takazawa, Yasumasa Tsukamoto, Kan Takeuchi, Koji Shibutani. 201-204 [doi]
- A 0.44V-1.1V 9-transistor transition-detector and half-path error detection technique for low power applicationsXinchao Shang, Weiwei Shan, Longxing Shi, Xing Wan, Jun Yang. 205-208 [doi]
- HTD: A light-weight holosymmetrical transition detector based in-situ timing monitoring technique for wide-voltage-range in 40nm CMOSWentao Dai, Weiwei Shan, Xinning Liu, Jun Yang. 209-212 [doi]
- A 0.5 V 12-bit SAR ADC using adaptive timedomain comparator with noise optimizationChen-Che Kao, Sung-En Hsieh, Chih-Cheng Hsieh. 213-216 [doi]
- Range pre-selection sampling technique to reduce input drive energy for SAR ADCsHarijot Singh Bindra, Joeri Lechevallier, Anne-Johan Annema, Simon M. Louwsma, Ed van Tuijl, Bram Nauta. 217-220 [doi]
- A 5-bit 2 GS/s binary-search ADC with charge-steering comparatorsU. Fat Chio, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins. 221-224 [doi]
- A 13-bit 160MS/s pipelined subranging-SAR ADC with low-offset dynamic comparatorWeitao Li, Fule Li, Jia Liu, HongYu Li, Zhihua Wang. 225-228 [doi]
- A 1.5fJ/conv-step 10b 100kS/s SAR ADC with gain-boosted dynamic comparatorXiyuan Tang, Long Chen 0004, Jeonggoo Song, Nan Sun. 229-232 [doi]
- 2 718GOPS configurable spiking convolutional sparse coding processor in 40nm CMOSChester Liu, Sung-gun Cho, Zhengya Zhang. 233-236 [doi]
- A 21mW low-power recurrent neural network accelerator with quantization tables for embedded deep learning applicationsJinmook Lee, Dongjoo Shin, Hoi-Jun Yoo. 237-240 [doi]
- 2 area in 40nm CMOSAnastacia B. Alvarez, Gopalakrishnan Ponnusamy, Massimo Alioto. 241-244 [doi]
- A self-powered always-on vision-based wake-up detector for wearable gesture user interfacesSuhwan Cho, Seongrim Choi, Junsik Woo, Ara Kim, Byeong-Gyu Nam. 245-248 [doi]
- A 18-to-23 GHz -253.5dB-FoM sub-harmonically injection-locked ADPLL with ILFD aided adaptive injection timing alignment techniqueZhao Zhang, Jincheng Yang, Liyuan Liu, Peng Feng, Jian Liu, Nanjian Wu. 249-252 [doi]
- A 1.5-GHz sub-sampling fractional-N PLL for spread-spectrum clock generator in 0.18-μm CMOSChun-Yu Lin, Tun-Ju Wang, Tsung-Hsien Lin. 253-256 [doi]
- A 2.1Gbps 12-channel transmitter with phase emphasis embedded serializer for UHD intra-panel interfaceJihwan Park, Joo-Hyung Chae, Yong-Un Jeong, Jae-Whan Lee, Suhwan Kim. 257-260 [doi]
- A low-power dual-mode 20-Gb/s NRZ and 28-Gb/s PAM-4 voltage-mode transmitterHae-Woong Yang, Ashkan Roshan-Zamir, Young-Hoon Song, Samuel Palermo. 261-264 [doi]
- Subthreshold voltage reference with nwell/psub diode leakage compensation for low-power high-temperature systemsInhee Lee, Dennis Sylvester, David Blaauw. 265-268 [doi]
- A smart-offset analog LDO with 0.3V minimum input voltage and 99.1% current efficiencySaurabh Chaubey, Ramesh Harjani. 269-272 [doi]
- A 762-pW 16.3-ps resolution digital pulse width modulator using zooming phase-interpolatorMasanobu Tsuji. 273-276 [doi]
- Fully-integrated AMLED micro display system with a hybrid voltage regulatorJunmin Jiang, Liusheng Sun, Xu Zhang, Shing Hin Yuen, Xianbo Li, Wing-Hung Ki, C. Patrick Yue, Kei May Lau. 277-280 [doi]
- A low-voltage low-offset dual strong-arm latch comparatorAikaterini Papadopoulou, Vladimir Milovanovic, Borivoje Nikolic. 281-284 [doi]
- A 5.35 mW 10 MHz bandwidth CT third-order ΔΣ modulator with single Opamp achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOSWei Wang, Yan Zhu 0001, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins. 285-288 [doi]
- A 72.9-dB SNDR 20-MHz BW 2-2 discrete-time sturdy MASH delta-sigma modulator using source-follower-based integratorsYong-Sik Kwak, Kang-Il Cho, Ho-Jin Kim, Seung-Hoon Lee, Gil-Cho Ahn. 289-292 [doi]
- A compact 87.1-dB DR bandwidth-scalable delta-sigma modulator based on dynamic gain-bandwidth-boosting inverter for audio applicationsYoung Ha Hwang, Jun-Eun Park, Deog Kyoon Jeong. 293-296 [doi]
- A 172dB-FoM pipelined SAR ADC using a regenerative amplifier with self-timed gain control and mixed-signal background calibrationMiguel Gandara, Paridhi Gulati, Nan Sun. 297-300 [doi]
- A fully-synthesizable C-element based PUF featuring temperature variation compensation with native 2.8% BER, 1.02fJ/b at 0.8-1.0V in 40nmSachin Taneja, Anastacia B. Alvarez, Gopalakrishnan Sadagopan, Massimo Alioto. 301-304 [doi]
- k FFT accelerator integrated with a RISC-V core in 16nm FinFETAngie Wang, Brian C. Richards, Palmer Dabbelt, Howard Mao, Stevo Bailey, Jaeduk Han, Eric Chang, James Dunn, Elad Alon, Borivoje Nikolic. 305-308 [doi]
- A 65nm 376nA 0.4V linear classifier using time-based matrix-multiplying ADC with non-linearity aware trainingAmaravati Anvesha, Arijit Raychowdhury. 309-312 [doi]
- A 1GHz fault tolerant processor with dynamic lockstep and self-recovering cache for ADAS SoC complying with ISO26262 in automotive electronicsJinho Han, Youngsu Kwon, Yong Cheol Peter Cho, Hoi-Jun Yoo. 313-316 [doi]
- A 77-GHz mixed-mode FMCW signal generator based on bang-bang phase detectorJianfu Lin, Zheng Song, Nan Qi, Woogeun Rhee, Baoyong Chi. 317-320 [doi]
- A 7GHz-bandwidth 31.5 GHz FMCW-PLL with novel twin-VCOs structure in 65nm CMOSShunli Ma, Jili Sheng, Ning Li, Junyan Ren. 321-324 [doi]
- A -245 dB FOM 48 fs rms jitter semi-digital PLL with intrinsic temperature compensation in 130 nm CMOSJens Anders, Sebastian Bader 0003, Markus Dietl, Puneet Sareen, G. Rombach, S. Tambouris, Maurits Ortmanns. 325-328 [doi]
- An ultra-low phase noise all-digital multi-frequency generator using injection-locked DCOs and time-interleaved calibrationSuneui Park, Heein Yoon, Jaehyouk Choi. 329-332 [doi]