Loop-based interconnect modeling and optimization approach for multigigahertz clock network design - researchr publication

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Xuejue Huang, Phillip J. Restle, Thomas J. Bucelot, Yu Cao, Tsu-Jae King 0001, Chenming Hu. Loop-based interconnect modeling and optimization approach for multigigahertz clock network design. J. Solid-State Circuits, 38(3):457-463, 2003. [doi]

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