Loop-based interconnect modeling and optimization approach for multigigahertz clock network design - researchr publication authors

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Xuejue Huang, Phillip J. Restle, Thomas J. Bucelot, Yu Cao, Tsu-Jae King 0001, Chenming Hu. Loop-based interconnect modeling and optimization approach for multigigahertz clock network design. J. Solid-State Circuits, 38(3):457-463, 2003. [doi]

This author has not been identified. Look up 'Xuejue Huang' in GoogleThis author has not been identified. Look up 'Phillip J. Restle' in GoogleThis author has not been identified. Look up 'Thomas J. Bucelot' in GoogleThis author has not been identified. Look up 'Yu Cao' in GoogleThis author has not been identified. Look up 'Tsu-Jae King 0001' in GoogleThis author has not been identified. Look up 'Chenming Hu' in Google

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