Loop-based interconnect modeling and optimization approach for multi-GHz clock network design - researchr publication

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Xuejue Huang, Phillip J. Restle, Thomas J. Bucelot, Yu Cao, Tsu-Jae King 0001. Loop-based interconnect modeling and optimization approach for multi-GHz clock network design. In Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, CICC 2002, Orlando, FL, USA, May 12-15, 2002. pages 19-22, IEEE, 2002. [doi]

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