Atsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe. A 47% access time reduction with a worst-case timing-generation scheme utilizing a statistical method for ultra low voltage SRAMs. In Symposium on VLSI Circuits, VLSIC 2012, Honolulu, HI, USA, June 13-15, 2012. pages 100-101, IEEE, 2012. [doi]
Abstract is missing.