Akihide Sai, Yuka Kobayashi, Shigehito Saigusa, Osamu Watanabe, Tetsuro Itakura. A digitally stabilized type-III PLL using ring VCO with 1.01psrms integrated jitter in 65nm CMOS. In 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012, San Francisco, CA, USA, February 19-23, 2012. pages 248-250, IEEE, 2012. [doi]
Abstract is missing.