Akihide Sai, Yuka Kobayashi, Shigehito Saigusa, Osamu Watanabe, Tetsuro Itakura. A digitally stabilized type-III PLL using ring VCO with 1.01psrms integrated jitter in 65nm CMOS. In 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012, San Francisco, CA, USA, February 19-23, 2012. pages 248-250, IEEE, 2012. [doi]
@inproceedings{SaiKSWI12,
title = {A digitally stabilized type-III PLL using ring VCO with 1.01psrms integrated jitter in 65nm CMOS},
author = {Akihide Sai and Yuka Kobayashi and Shigehito Saigusa and Osamu Watanabe and Tetsuro Itakura},
year = {2012},
doi = {10.1109/ISSCC.2012.6176996},
url = {http://dx.doi.org/10.1109/ISSCC.2012.6176996},
researchr = {https://researchr.org/publication/SaiKSWI12},
cites = {0},
citedby = {0},
pages = {248-250},
booktitle = {2012 IEEE International Solid-State Circuits Conference, ISSCC 2012, San Francisco, CA, USA, February 19-23, 2012},
publisher = {IEEE},
isbn = {978-1-4673-0376-7},
}