He Gong Wei - researchr alias

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Viewing Publication 1 - 16 from 16

2020

A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch CalibrationMingqiang Guo, Jiaji Mao, Sai-Weng Sin, He Gong Wei, Rui P. Martins. jssc, 55(3):693-705, 2020. [doi]

A 5 GS/s 29 mW Interleaved SAR ADC With 48.5 dB SNDR Using Digital-Mixing Background Timing-Skew Calibration for Direct Sampling ApplicationsMingqiang Guo, Jiaji Mao, Sai-Weng Sin, He Gong Wei, Rui Paulo Martins. access, 8:138944-138954, 2020. [doi]

2019

A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR With Fully-Digital Timing-Skew Calibration Based on Digital-MixingMingqiang Guo, Jiaji Mao, Sai-Weng Sin, He Gong Wei, Rui Paulo Martins. vlsic 2019: 76 [doi]

A 10b 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch CalibrationMingqiang Guo, Jiaji Mao, Sai-Weng Sin, He Gong Wei, Rui Paulo Martins. cicc 2019: 1-4 [doi]

2012

2011

2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOSHe Gong Wei, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti. isscc 2011: 188-190 [doi]

2010

Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADCU-Fat Chio, He Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti. tcas, 57-II(8):607-611, 2010. [doi]

An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&HSai-Weng Sin, Li Ding, Yan Zhu 0001, He Gong Wei, Chi-Hang Chan, U. Fat Chio, Seng-Pan U, Rui P. Martins, Franco Maloberti. esscirc 2010: 218-221 [doi]

A Rapid Power-Switchable Track-and-Hold Amplifier in 90-nm CMOSHe Gong Wei, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins. tcas, 57-II(1):16-20, 2010. [doi]

An ultra low power 9-bit 1-MS/s pipelined SAR ADC for bio-medical applicationsGuohe Yin, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Zhihua Wang. icecsys 2010: 878-881 [doi]

Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCsYan Zhu, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins. vlsi, 2010, 2010. [doi]

2008

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