Tetsuya Fujita - researchr alias

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Viewing Publication 1 - 16 from 16

2013

Improvement of Factor Model with Text Information Based on Factor Model Construction ProcessRyosuke Saga, Tetsuya Fujita, Kodai Kitami, Kazunori Matsumoto. iimss 2013: 222-230 [doi]

2011

A 7uW deep-sleep, ultra low-power WLAN baseband LSI for mobile applicationsDaisuke Taki, Tatsuo Shiozawa, Kuniaki Ito, Youichiro Shiba, Kouji Horisaki, Hirotsugu Kajihara, Toshiyuki Yamagishi, Masahiro Sekiya, Akira Yamaga, Tetsuya Fujita, Hiroyuki Hara, Masanori Kuwahara, Toshio Fujisawa, Yasuo Unekawa. coolchips 2011: 1-3 [doi]

A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40nm CMOSChen Kong Teh, Tetsuya Fujita, Hiroyuki Hara, Mototsugu Hamada. isscc 2011: 338-340 [doi]

2010

A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nmYu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Yukihito Oowaki. isscc 2010: 326-327 [doi]

2009

2008

2006

2005

A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSIMototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Chen Kong Teh, Takayoshi Shimazawa, Naoyuki Kawabe, Takeshi Kitahara, Yu Kikuchi, Tsuyoshi Nishikawa, Makoto Takahashi, Yukihito Oowaki. cicc 2005: 527-530 [doi]

2003

A single-chip 802.11a MAC/PHY with a 32-b RISC processorToshio Fujisawa, Jun Hasegawa, Koji Tsuchie, Tatsuo Shiozawa, Tetsuya Fujita, Toshitada Saito, Yasuo Unekawa. jssc, 38(11):2001-2009, 2003. [doi]

1998

1996

1988

MASA: A Multithreaded Processor Architecture for Parallel Symbolic ComputingRobert H. Halstead Jr., Tetsuya Fujita. isca 1988: 443-451

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