Akihiko Chiba - researchr alias

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Viewing Publication 1 - 4 from 4

1998

A top-down low power design technique using clustered voltage scaling with variable supply-voltage schemeMototsugu Hamada, Masafumi Takahashi, Hideho Arakida, Akihiko Chiba, Toshihiro Terazawa, Takashi Ishikawa, Masahiro Kanazawa, Mutsunori Igarashi, Kimiyoshi Usami, Tadahiro Kuroda. cicc 1998: 495-498 [doi]

Variable supply-voltage scheme for low-power high-speed CMOS digital designTadahiro Kuroda, Kojiro Suzuki, Shinji Mita, Tetsuya Fujita, Fumiyuki Yamane, Fumihiko Sano, Akihiko Chiba, Yoshinori Watanabe, Koji Matsuda, Takeo Maeda, Takayasu Sakurai, Tohru Furuyama. jssc, 33(3):454-462, 1998. [doi]

1994

A 200 MHz 13 mm/sup 2/ 2-D DCT macrocell using sense-amplifying pipeline flip-flop schemeMasataka Matsui, Hiroyuki Hara, Yoshiharu Uetani, Lee-Sup Kim, Tetsu Nagamatsu, Yoshinori Watanabe, Akihiko Chiba, Kouji Matsuda, Takayasu Sakurai. jssc, 29(12):1482-1490, December 1994. [doi]

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