Table of Contents

• The design of a high performance low power microprocessorDan Dobberpuhl. 11-16 [doi]
• Low power systems for wireless microsensorsK. Bult, Amit Burstein, D. Chang, Michael J. Dong, M. Fielding, E. Kruglick, J. Ho, F. Lin, T. Lin, William J. Kaiser, H. Marcy, R. Mukai, Phyllis R. Nelson, F. Newburg, Kristofer S. J. Pister, Gregory J. Pottie, Henry Sanchez, Oscar M. Stafsudd, K. Tan, S. Xue, J. Yao. 17-21 [doi]
• A low power architecture for wireless multimedia systems: lessons learned from building a power hogWilliam H. Mangione-Smith, Phil Seong Ghang, Sean Nazareth, Paul Lettieri, Walt Boring, Rajeev Jain. 23-28 [doi]
• High-level power estimationPaul E. Landman. 29-35 [doi]
• A power metric for mobile systemsThomas L. Martin, Daniel P. Siewiorek. 37-42 [doi]
• Lower bounds on power dissipation for DSP algorithmsNaresh R. Shanbhag. 43-48 [doi]
• A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemesHiroyuki Yamauchi, Toru Iwata, Hironori Akamatsu, Akira Matsuzawa. 49-54 [doi]
• Energy recovery for the design of high-speed, low-power static RAMsNestoras Tzartzanis, William C. Athas. 55-60 [doi]
• A 1-V 1-Mb SRAM for portable equipmentHiroki Morimura, Nobutaro Shibata. 61-66 [doi]
• A novel methodology for transistor-level power estimationShi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Mike Tien-Chien Lee. 67-72 [doi]
• Statistical estimation of average power dissipation in CMOS VLSI circuits using nonparametric techniquesLi-Pen Yuan, Chin-Chi Teng, Sung-Mo Kang. 73-78 [doi]
• Switching activity analysis for sequential circuits using Boolean approximation methodTaku Uchino, Fumihiro Minami, Masami Murakata, Takashi Mitsuhashi. 79-84 [doi]
• Transition reduction in carry-save adder treesPatrik Larsson, Chris J. Nicol. 85-88 [doi]
• 250-600 Mhz 12b digital filters in 0.8-0.25um Bulk and SOI CMOS technologiesLars E. Thon, Ghavam G. Shahidi, Werner Rausch, Gerald P. Coleman, Denny D. Tang, Dominic Schepis, Ronald Schulz, Fariborz Assadaraghi. 89-92 [doi]
• A comparison of CMOS implementations of an asynchronous circuits primitive: the C-elementMaitham Shams, Jo C. Ebergen, Mohamed I. Elmasry. 93-96 [doi]
• Design techniques for high performance, energy efficient control logicUming Ko, Anthony M. Hill, Poras T. Balsara. 97-100 [doi]
• Energy-recovery CMOS for highly pipelined DSP designsWilliam C. Athas, W. C. Liu, Lars J. Svensson. 101-104 [doi]
• Gate-level current waveform simulation of CMOS integrated circuitsAlessandro Bogliolo, Luca Benini, Giovanni De Micheli, Bruno Riccò. 109-112 [doi]
• Effects of correlations on accuracy of power analysis - an experimental studyPeter H. Schneider, Shankar Krishnamoorthy. 113-116 [doi]
• Basic experimentation on accuracy of power estimation for CMOS VLSI circuitsTohru Ishihara, Hiroto Yasuura. 117-120 [doi]
• Simulation based architectural power estimation for PLA-based controllersSrinivas Katkoori, Ranga Vemuri. 121-124 [doi]
• Short circuit power consumption of glitchesDirk Rabe, Wolfgang Nebel. 125-128 [doi]
• A graded-channel MOS (GCMOS) VLSI technology for low power DSP applicationsJun Ma, Han-Bin Liang, Michael Kaneshiro, Carl Kyono, Robert Pryor, Ken Papworth, Sunny Cheng. 129-132 [doi]
• Fabrication and performance of mesa interconnectL. Richard Carley, David F. Guillou, Suresh Santhanam. 133-137 [doi]
• Floating body effects in partially-depleted SOI CMOS circuitsP. Lu, J. Ji, C. Chuang, L. Wagner, C. Hsieh, J. Kuang, L. Hsu, M. Pelella, S. Chu, C. Anderson. 139-144 [doi]
• An investigation of the impact of technology scaling on power wasted as short-circuit current in low voltage static CMOS circuitsAmitava Chatterjee, Mahalingam Nandakumar, Ih-Chin Chen. 145-150 [doi]
• Concurrency-oriented optimization for low-power asynchronous systemsLuis A. Plana, Steven M. Nowick. 151-156 [doi]
• Energy minimization using multiple supply voltagesJui-Ming Chang, Massoud Pedram. 157-162 [doi]
• Symbolic computation of logic implications for technology-dependent low-power synthesisR. Iris Bahar, M. Burns, Gary D. Hachtel, Enrico Macii, H. Shin, Fabio Somenzi. 163-168 [doi]
• Integrated resynthesis for low powerOlivier Coudert, Ramsey W. Haddad. 169-174 [doi]
• Which has greater potential power impact: high-level design and algorithms or innovative low power technology? (panel)James Burr, Laszlo Gal, Ramsey W. Haddad, Jan M. Rabaey, Bruce Wooley. 175 [doi]
• How to design low-power digital cellular phonesKoichiro Mashiko. 177-180 [doi]
• What is the state of the art in commercial EDA tools for low power?Kurt Keutzer, Olivier Coudert, Ramsey W. Haddad. 181-187 [doi]
• Accurate evaluation of CMOS short-circuit power dissipation for short-channel devicesLabros Bisdounis, Odysseas G. Koufopavlou, Spiridon Nikolaidis. 189-192 [doi]
• Circuit techniques for low-power CMOS GSIAzeez J. Bhavnagarwala, Vivek De, Blanca Austin, James D. Meindl. 193-196 [doi]
• Device design for low power electronics with accurate deep submicrometer LDD-MOSFET modelsKai Chen 0002, Yuhua Cheng, Chenming Hu. 197-200 [doi]
• Energy delay analysis of partial product reduction methods for parallel multiplier implementationR. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili. 201-204 [doi]
• Low-power radix-4 dividerAlberto Nannarelli, Tomás Lang. 205-208 [doi]
• Power comparisons for barrel shiftersKevin P. Acken, Mary Jane Irwin, Robert Michael Owens. 209-212 [doi]
• Interlaced accumulation programming for low power DSPHirotsugu Kojima, Avadhani Shridhar. 213-216 [doi]
• Low-power adaptive filter architectures via strength reductionManish Goel, Naresh R. Shanbhag. 217-220 [doi]
• Leap frog multiplierShivaling S. Mahant-Shetti, Carl Lemonds, Poras T. Balsara. 221-223 [doi]
• Manufacturability of low power CMOS technology solutionsAndrzej J. Strojwas, Michele Quarantelli, J. Borel, Carlo Guardiani, G. Nicollini, G. Crisenza, Bruno Franzini, J. Wiart. 225-232 [doi]
• Effects of random MOSFET parameter fluctuations on total power consumptionXinghai Tang, Vivek De, James D. Meindl. 233-236 [doi]
• The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuitsM. Eisele, Jörg Berthold, Doris Schmitt-Landsiedel, R. Mahnkopf. 237-242 [doi]
• 12-b 125 MSPS CMOS D/A designed for spectral performanceDouglas Mercer, Larry Singer. 243-246 [doi]
• Implementation of a micro power 15-bit floating-point A/D converterL. Grisoni, Alexandre Heubi, Peter Balsiger, Fausto Pellandini. 247-252 [doi]
• Micro power relative precision 13 bits cyclic RSD A/D converterAlexandre Heubi, Peter Balsiger, Fausto Pellandini. 253-257 [doi]
• Fixed-phase retiming for low power designMarios C. Papaefthymiou, Kumar N. Lalgudi. 259-264 [doi]
• Clock skew optimization for peak current reductionPatrick Vuillod, Luca Benini, Alessandro Bogliolo, Giovanni De Micheli. 265-270 [doi]
• Simultaneous buffer and wire sizing for performance and power optimizationJason Cong, Cheng-Kok Koh, Kwok-Shing Leung. 271-276 [doi]
• A low power high performance switched-current multiplierDomine Leenaerts, G. H. M. Joordens, J. A. Hegt. 277-280 [doi]
• Low-power frequency multiplier with one cycle lock-in time and 100ppm frequency resolution, for system power-managementRafael Fried, Ziv Azmanov. 281-284 [doi]
• A 1.5V class AB output bufferFan You, Sherif H. K. Embabi, Edgar Sánchez-Sinencio. 285-288 [doi]
• Low-power mapping of behavioral arrays to multiple memoriesPreeti Ranjan Panda, Nikil D. Dutt. 289-292 [doi]
• Logic synthesis using power-sensitive don t care setsChristopher K. Lennard, Premal Buch, A. Richard Newton. 293-296 [doi]
• Gate-level synthesis for low-power using new transformationsDhiraj K. Pradhan, Mitrajit Chatterjee, Madhu V. Swarna, Wolfgang Kunz. 297-300 [doi]
• Controller re-specification to minimize switching activity in controller/data path circuitsAnand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi. 301-304 [doi]
• A 200 µA, 78 MHz CMOS crystal-oscillator digitally trimmable to 0.3 ppmQiuting Huang, Philipp Basedau. 305-308 [doi]
• Substrate noise influence on circuit performance in variable threshold-voltage schemeTadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Toshiaki Mori, Kenji Matsuo, Masakazu Kakumu, Takayasu Sakurai. 309-312 [doi]
• A low power switching power supply for self-clocked systemsGu-Yeon Wei, Mark Horowitz. 313-317 [doi]
• Design of a programmable temperature monitoring device for tagging small fishGodi Fischer, James C. Daly, Chun Yang, Conrad W. Recksiek, Kevin D. Friedland. 319-322 [doi]
• Entropic bounds on FSM switchingAkhilesh Tyagi. 323-328 [doi]
• High-level power estimation and the area complexity of Boolean functionsMahadevamurty Nemani, Farid N. Najm. 329-334 [doi]
• Two dimensional codes for low powerMircea R. Stan, Wayne P. Burleson. 335-340 [doi]
• Low power, testable dual edge triggered flip-flopsRafael Llopis, Manoj Sachdev. 341-345 [doi]
• Data driven signal processing: an approach for energy efficient computingAnantha Chandrakasan, Vadim Gutnik, Thucydides Xanthopoulos. 347-352 [doi]
• Stage-skip pipeline: a low power processor architecture using a decoded instruction bufferMitsuru Hiraki, Raminder Singh Bajwa, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Katsuro Sasaki, Koichi Seki. 353-358 [doi]
• Power exploration for data dominated video applicationsSven Wuytack, Francky Catthoor, Lode Nachtergaele, Hugo De Man. 359-364 [doi]
• Practical performance/power alternatives within an existing CMOS technology generationKerry Bernstein, John E. Bertsch, William F. Clark, John J. Ellis-Monaghan, Larry G. Heller, Edward J. Nowak. 365-370 [doi]
• A dynamic energy recycling logic family for ultra-low-power gigascale integration (GSI)Vivek De, James D. Meindl. 371-375 [doi]
• Comparison of high speed voltage-scaled conventional and adiabatic circuitsDavid J. Frank. 377-380 [doi]
• Static power driven voltage scaling and delay driven buffer sizing in mixed swing QuadRail for sub-1V I/O swingsRam K. Krishnamurthy, Ihor Lys, L. Richard Carley. 381-386 [doi]