Edward J. Nowak - researchr alias

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Viewing Publication 1 - 18 from 18

2018

A Retrospective View on the Technology Evolution to Support Low Power Mobile ApplicationBipul C. Paul, Ajey P. Jacob, William Taylor, Randy W. Mann, Joseph Versaggi, Edward J. Nowak, Lars W. Liebmann. jolpe, 14(3):374-392, 2018. [doi]

2008

Compact modeling and simulation of PD-SOI MOSFETs: Current status and challengesJung-Suk Goo, Richard Q. Williams, Glenn O. Workman, Qiang Chen, Sungjae Lee, Edward J. Nowak. cicc 2008: 265-272 [doi]

2007

A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET TechnologyRajiv V. Joshi, Keunwoo Kim, Richard Q. Williams, Edward J. Nowak, Ching-Te Chuang. vlsid 2007: 665-672 [doi]

2006

2005

Status and Direction of Communication Technologies - SiGe BiCMOS and RFCMOSAlvin J. Joseph, David L. Harame, Basanth Jagannathan, Douglas D. Coolbaugh, David C. Ahlgren, John Magerlein, Louis D. Lanzerotti, Natalie B. Feilchenfeld, Stephen A. St. Onge, James S. Dunn, Edward J. Nowak. pieee, 93(9):1539-1558, 2005. [doi]

2003

2002

Maintaining the benefits of CMOS scaling when scaling bogs downEdward J. Nowak. ibmrd, 46(2-3):169-186, 2002. [doi]

CMOS scaling beyond the 100-nm node with silicon-dioxide-based gate dielectricsErnest Y. Wu, Edward J. Nowak, Alex Vayshenker, Wing L. Lai, David L. Harmon. ibmrd, 46(2-3):287-298, 2002. [doi]

2001

Device scaling limits of Si MOSFETs and their application dependenciesDavid J. Frank, Robert H. Dennard, Edward J. Nowak, Paul M. Solomon, Yuan Taur, Hon-Sum Philip Wong. pieee, 89(3):259-288, 2001. [doi]

1996

Practical performance/power alternatives within an existing CMOS technology generationKerry Bernstein, John E. Bertsch, William F. Clark, John J. Ellis-Monaghan, Larry G. Heller, Edward J. Nowak. islped 1996: 365-370 [doi]

1995

Reduced-voltage power/performance optimization of the 3.6-volt PowerPC 601 MicroprocessorKerry Bernstein, John E. Bertsch, Lawrence G. Heller, Edward J. Nowak, Francis R. White. ibmrd, 39(1-2):33-42, 1995.

Overview of gate linewidth control in the manufacture of CMOS logic chipsDonald G. Chesebro, James W. Adkisson, Lyman R. Clark, Steven N. Eslinger, Margaret A. Faucher, Steven J. Holmes, Raymond P. Mallette, Edward J. Nowak, Edward W. Sengle, Steven H. Voldman, Thomas W. Weeks. ibmrd, 39(1-2):189-200, 1995.

CMOS scaling into the 21st century: 0.1 µm and beyondYuan Taur, Yuh-Jier Mii, David J. Frank, H.-S. Philip Wong, Douglas A. Buchanan, Shalom J. Wind, Stephen A. Rishton, Watson A. Sai-Halasz, Edward J. Nowak. ibmrd, 39(1-2):245-260, 1995.

1994

MOSFET technology for low-voltage/low-power applicationsDaniel Foty, Edward J. Nowak. micro, 14(3):68-77, 1994. [doi]

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