Abstract is missing.
- Session 10 - Panel discussion Sure, Moore's Law can continue, but should itDavid A. Sunderland, Kazuyuki Kawauchi, John Kent, Randy Mooney, Chuck Moore, Clark T.-C. Nguyen. [doi]
- Session 2 - Statistical modelingHidetoshi Onodera, Hong-Ha Vuong. [doi]
- Session 15 - IC Technology - more Moore and more than MooreAlvin Loke, Jordan Lai. [doi]
- Session 20 - Advanced wireline techniquesEd van Tuijl, Ken Chang. [doi]
- Session 16 - Embedded memoryKenji Noda, Jean-Christophe Vial. [doi]
- Session 17 - Clocking circuitsDennis Michael Fischette, Kimo Tam. [doi]
- Session 18 - Millimeter-wave circuit techniquesPayam Heydari, Nobuyuki Itoh. [doi]
- Session 13 - Biomedical, sensors and MEMSMakoto Nagata, Steven L. Garverick. [doi]
- Session 24 - Advanced subsystems for connectivity and cellular radioStefan Drude, Earl McCune. [doi]
- More than MooreDave Bergeron. [doi]
- Session 6 - Advanced SoC/SiP integration & co-designRich Liu, Philippe Jansen. [doi]
- Session 14 - Advanced SoCs - techniques and applicationsSteve Wilton, Arif Rahman. [doi]
- Session 23 - Analog techniquesDon Thelen, Ken Suyama. [doi]
- Session 22 - Noise and oscillator simulationColin McAndrew, Larry Nagel. [doi]
- Session 9 - Broadband circuit techniques for emerging wireless communicationsFa Foster Dai, Howard Luong. [doi]
- Session 4 - High-speed test, characterization, and debugMike Li, Gordon Roberts. [doi]
- Session 11 - Compact modelingGennady Gildenblat, Brian Chen. [doi]
- Session 19 - Low power and non-traditional RF tranceiversRamesh Harjani, Andrea Mazzanti. [doi]
- Session 3 - Power managementGordon Lee, Makoto Takamiya. [doi]
- Session 7 - High resolution convertersYusuf Haque, George LaRue. [doi]
- Session 8 - Characterization and test methods for device variability in nanoscale technologiesHamid Mahmoodi, Jeanne Trinko Mechler. [doi]
- Session 5 - Broadband circuit techniques for emerging wireless communicationsFa Foster Dai, Howard Luong. [doi]
- Session 21 - Leveraging the third DimensionRakesh Patel, Michael Seningen. [doi]
- Process variability at the 65nm node and beyondSani R. Nassif. 1-8 [doi]
- Mismatch analysis and statistical design at 65 nm and belowLarry T. Pileggi, Gökçe Keskin, Xin Li, Ken Mai, Jonathan Proesel. 9-12 [doi]
- Statistical prediction of circuit aging under process variationsWenping Wang, Vijay Reddy, Bo Yang, Varsha Balakrishnan, Srikanth Krishnan, Yu Cao. 13-16 [doi]
- A fully-integrated 0.18μm CMOS DC-DC step-down converter, using a bondwire spiral inductorMike Wens, Michiel Steyaert. 17-20 [doi]
- A 90-240MHz hysteretic controlled DC-DC buck converter with digital PLL frequency lockingPengfei Li, Deepak Bhatia, Lin Xue, Rizwan Bashirullah. 21-24 [doi]
- Fast transient technique (FTT) in buck current-mode DC-DC converters for low-voltage SoC systemsChia-Hsiang Lin, Hong-Wei Huang, Ke-Horng Chen. 25-28 [doi]
- A process variation compensation scheme using cell-based forward body-biasing circuits usable for 1.2V designFumihiko Tachibana, Hironori Sato, Takahiro Yamashita, Hiroyuki Hara, Takeshi Kitahara, Shuou Nomura, Fumiyuki Yamane, Yoshiro Tsuboi, Keiko Seki, Shuuji Matsumoto, Yoshinori Watanabe, Mototsugu Hamada. 29-32 [doi]
- Built-in resistance compensation (BRC) technique for fast charging Li-Ion battery chargerChia-Hsiang Lin, Hong-Wei Huang, Ke-Horng Chen. 33-36 [doi]
- A voltage drop aware crosstalk measurement with multi-aggressors in 65nm processGenichi Tanaka, Kan Takeuchi, Minoru Ito, Hiroaki Matsushita. 37-40 [doi]
- Measurements of the silicon die characteristics of packaged drivers for high-speed I/OGerry Talbot, Edoardo Prete. 41-48 [doi]
- Inductor-based ESD protection under CDM-like ESD stress conditions for RF applicationsSteven Thijs, Mototsugu Okushima, Jonathan Borremans, Philippe Jansen, Dimitri Linten, Mirko Scholz, Piet Wambacq, Guido Groeseneken. 49-52 [doi]
- Non-destructive IC defect localization using optical beam-based imagingEdward I. Cole Jr.. 53-56 [doi]
- Emerging application opportunities for SiGe technologyJohn D. Cressler. 57-64 [doi]
- A 0.8GHz-10.6GHz SDR low-noise amplifier in 0.13-μm CMOSShuzuo Lou, Howard C. Luong. 65-68 [doi]
- A 1.3-6 GHz triple-mode CMOS VCO using coupled inductorsZahra Safarian, Hossein Hashemi. 69-72 [doi]
- A SOC/SOP co-design approach for mmW CMOS in QFN technologyJoy Laskar, Stephane Pinel, Saikat Sarkar, Padmanava Sen, Bevin G. Perunama, Debasis Dawn, David Yeh, Francesco Barale. 73-80 [doi]
- Chip to carrier C4 technology challenges with Pb free soldersEric D. Perfecto, Brian Sundlof, Kamalesh Srivastava, Minhua Lu. 81-84 [doi]
- A study on process-compatibility in CMOS-first MEMS-last integrationKazuhiro Takahashi, Makoto Mita, Hiroyuki Fujita, Kazuhiro Suzuki, Hideyuki Funaki, Kazuhiko Itaya, Hiroshi Toshiyoshi. 85-88 [doi]
- A 101-dB SNR hybrid delta-sigma audio ADC using post integration time controlMoo-Yeol Choi, Sung-No Lee, Seung-Bin You, Wang-Seup Yeum, Ho-Jin Park, Jae-Whui Kim, Hae-Seung Lee. 89-92 [doi]
- An 8.1 mW, 82 dB delta-sigma ADC with 1.9 MHz BW and -98 dB THDKyehyung Lee, Matthew R. Miller, Gabor C. Temes. 93-96 [doi]
- A 2.5MHz BW and 78dB SNDR delta-sigma modulator using dynamically biased amplifiersYan Wang, Kyehyung Lee, Gabor C. Temes. 97-100 [doi]
- 74dB SNDR multi-loop sturdy-MASH delta-sigma modulator using 35dB opamp gainNima Maghari, Sunwoo Kwon, Un-Ku Moon. 101-104 [doi]
- A/D converter trends: Power dissipation, scaling and digitally assisted architecturesBoris Murmann. 105-112 [doi]
- A 16b 10MS/s digitally self-calibrated ADC with time constant controlTae-Hwan Oh, Ho-Young Lee, Ju-Hwa Kim, Ho-Jin Park, Kyoung-Ho Moon, Jae-Whui Kim, Hae-Seung Lee. 113-116 [doi]
- A 15b power-efficient pipeline A/D converter using non-slewing closed-loop amplifiersShoji Kawahito, Kazutaka Honda, Zheng Liu, Keita Yasutomi, Shinya Itoh. 117-120 [doi]
- An array-based test circuit for fully automated gate dielectric breakdown characterizationJohn Keane, Shrinivas Venkatraman, Paulo F. Butzen, Chris H. Kim. 121-124 [doi]
- A high sensitivity process variation sensor utilizing sub-threshold operationMesut Meterelliyoz, Peilin Song, Franco Stellari, Jaydeep P. Kulkarni, Kaushik Roy. 125-128 [doi]
- Measurement and analysis of variability in 45nm strained-Si CMOS technologyLiang-Teck Pang, Borivoje Nikolic. 129-132 [doi]
- Within-die gate delay variability measurement using re-configurable ring oscillatorBishnu Prasad Das, Bharadwaj Amrutur, H. S. Jamadagni, N. V. Arvind, V. Visvanathan. 133-136 [doi]
- Expected vectorless Teacher-Student Swap (TSS) test method with dual power supply voltages for 0.3V homogeneous multi-core LSI'sTaro Niiyama, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai. 137-140 [doi]
- MIMO techniques for high data rate radio communicationsYorgos Palaskas, Ashoke Ravi, Stefano Pellerano. 141-148 [doi]
- Wireless interconnection within a hybrid engine controller boardSwaminathan Sankaran, Kyujin Oh, Hsin-Ta Wu, Kenneth K. O. 149-152 [doi]
- A 0.6-to-1V inverter-based 5-bit flash ADC in 90nm digital CMOSJonathan Proesel, Lawrence T. Pileggi. 153-156 [doi]
- A 10∼15b 60MS/s floating-point ADC with digital gain and offset calibrationYun-Shiang Shu, Moon-Jung Kyung, Wei-Ming Lee, Bang-Sup Song, Bedabrata Pain. 157-160 [doi]
- Digital correction of dynamic track-and-hold errors providing SFDR ≫ 83 dB up to fin = 470 MHzParastoo Nikaeen, Boris Murmann. 161-164 [doi]
- A 65nm CMOS 1.2V 12b 30MS/s ADC with capacitive reference scalingKang-Jin Lee, Kyoung-Jun Moon, Kwang-Sung Ma, Kyoung-Ho Moon, Jae-Whui Kim. 165-168 [doi]
- A continuous-time input pipeline ADCDavid Gubbins, Bumha Lee, Pavan Kumar Hanumolu, Un-Ku Moon. 169-172 [doi]
- A 0.8 V asynchronous ADC for energy constrained sensing applicationsMichael Trakimas, Sameer R. Sonkusale. 173-176 [doi]
- Modeling, design and optimization of hybrid electromagnetic and piezoelectric MEMS energy scavengersXiaochun Wu, Alireza Khaligh, Yang Xu. 177-180 [doi]
- Amorphous silicon logic circuits on flexible substratesRahul Shringarpure, Lawrence T. Clark, Sameer M. Venugopal, David R. Allee, Shrinivas G. Uppili. 181-184 [doi]
- Frequency tunable silicon carbide resonators for MEMS above ICFrederic Nabki, Tomas A. Dusatko, Mourad N. El-Gamal. 185-188 [doi]
- MEMS wafer-level vacuum packaging with transverse interconnects for CMOS integrationDominique Lemoine, Paul-Vahe Cicek, Frederic Nabki, Mourad N. El-Gamal. 189-192 [doi]
- Variation-tolerant Spin-Torque Transfer (STT) MRAM array for yield enhancementJing Li, Haixin Liu, Sayeef S. Salahuddin, Kaushik Roy. 193-196 [doi]
- Pure logic CMOS based embedded Non-Volatile Random Access Memory for low power RFID applicationLiyang Pan, Xian Luo, Yaru Yan, Jirong Ma, Dong Wu, Jun Xu. 197-200 [doi]
- A high-speed, low-power 3D-SRAM architectureH. Henry Nho, Mark Horowitz, S. Simon Wong. 201-204 [doi]
- Early prediction of product performance and yield via technology benchmarkChoongyeun Cho, Daeik D. Kim, Jonghae Kim, Daihyun Lim, Sangyeun Cho. 205-208 [doi]
- A FPGA vernier digital-to-time converter with 3.56ps resolution and -0.23∼+0.2LSB inaccuracyPoki Chen, Juan-Shan Lai, Po-Yu Chen. 209-212 [doi]
- RASP 2.8: A new generation of floating-gate based field programmable analog arrayArindam Basu, Christopher M. Twigg, Stephen Brink, Paul E. Hasler, Csaba Petre, Shubha Ramakrishnan, Scott Koziol, Craig Schlottmann. 213-216 [doi]
- Modeling of triple-well isolation and the loading effects on circuits up to 50 GHzPiljae Park, C. Patrick Yue. 217-220 [doi]
- A general weak nonlinearity model for LNAsWei Cheng, Anne-Johan Annema, Jeroen A. Croon, Dick B. M. Klaassen, Bram Nauta. 221-224 [doi]
- Modeling and synthesis of wide-band switched-resonators for VCOsBodhisatwa Sadhu, Umaikhe E. Omole, Ramesh Harjani. 225-228 [doi]
- Faster statistical cell characterization using adjoint sensitivity analysisBen Gu, Kiran K. Gullapalli, Yun Zhang, Savithri Sundareswaran. 229-232 [doi]
- An ESD-protected 5-GHz differential low-noise amplifier in a 130-nm CMOS processYuan-Wen Hsiao, Ming-Dou Ker. 233-236 [doi]
- A 65nm 3.4Gbps HDMI TX PHY with supply-regulated dual-tuning PLL and blending multiplexerJongshin Shin, Jaehyun Park, Bongjin Kim, Jongjae Ryu, Chiwon Kim, Jiyoung Kim, Seung-Hee Yang, Hyungoo Kim, Jaewhui Kim. 237-240 [doi]
- A scalable digitalized buffer for gigabit I/OHungwen Lu, Chauchin Su, Chien-Nan Liu. 241-244 [doi]
- Broadband transimpedance amplifier in 0.35-μm SiGe BiCMOS technology for 10-Gb/s optical receiver analog front-end applicationJi-Chen Huang, Yu-Sheng Lai, K. Hsu. 245-248 [doi]
- A multifunction transceiver RFIC for 802.11a/b/g WLAN and DVB-H applicationsYin Shi, Foster F. Dai, Jun Yan, Xueqing Hu, Hua Xu, Ming Gu, Xuelian Zhang, Qiming Xu, Bei Chen, Fangxiong Chen, Peng Yu, Heping Ma, Fang Yuan, Richard C. Jaeger. 249-252 [doi]
- A fully integrated zero-IF mobile TV tuner RFIC for S-band CMMB applicationYin Shi, Fa Foster Dai, Jun Yan, Hua Xu, Xuelian Zhang, Heping Ma, Fang Yuan, Xin Guan, Richard C. Jaeger. 253-256 [doi]
- Compact modeling of multiple-gate MOSFETsYuan Taur, Jooyoung Song, Bo Yu. 257-264 [doi]
- Compact modeling and simulation of PD-SOI MOSFETs: Current status and challengesJung-Suk Goo, Richard Q. Williams, Glenn O. Workman, Qiang Chen, Sungjae Lee, Edward J. Nowak. 265-272 [doi]
- Modeling ionizing radiation effects in solid state materials and CMOS devicesHugh J. Barnaby, Michael L. McLain, Ivan Sanchez Esqueda, Xiao J. Chen. 273-280 [doi]
- Characterization, simulation, and modeling of FET source/drain diffusion resistanceNing Lu, Bill Dewey. 281-284 [doi]
- Analysis of the impact of interfacial oxide thickness variation on metal-gate high-K circuitsMinki Cho, Kingsuk Maitra, Saibal Mukhopadhyay. 285-288 [doi]
- Time-interleaved analog-to-digital convertersDavid G. Nairn. 289-296 [doi]
- A 12b 50MSPS 34mW pipelined ADCHao Yu, Sing W. Chin, Bill C. Wong. 297-300 [doi]
- Background ADC calibration in digital domainCheongyuen W. Tsang, Yun Chiu, Johan P. Vanderhaegen, Sebastian Hoyos, Charles Chen, Robert W. Brodersen, Borivoje Nikolic. 301-304 [doi]
- A 1.2v 11b 100Msps 15mW ADC realized using 2.5b pipelined stage followed by time interleaved SAR in 65nm digital CMOS processPratap Narayan Singh, Ashish Kumar, Chandrajit Debnath, Rakesh Malik. 305-308 [doi]
- A 52mW 10b 210MS/s two-step ADC for digital-IF receivers in 0.13μm CMOSZhiheng Cao, Shouli Yan. 309-312 [doi]
- A 24GS/s 5-b ADC with closed-loop THA in 0.18μm SiGe BiCMOSJaesik Lee, Joseph Weiner, Pascal Roux, Andreas Leven, Young-Kai Chen. 313-316 [doi]
- A biomedical implantable FES battery-powered micro-stimulatorEusebiu Matei, Edward K. Lee, John Gord, Patrick Nercessian, Phil Hess, Howard Stover, Taihu Li, James Wolfe. 317-324 [doi]
- CMOS LSI-based multi-chip flexible retinal prosthesis device for subretinal implantationTakashi Tokuda, Shigeki Sawamura, Yasuo Terasawa, Yasuo Tano, Jun Ohta. 325-328 [doi]
- A CMOS TDC-based digital magnetic Hall sensor using the self temperature compensationYoung-Jae Min, Soo-Won Kim. 329-332 [doi]
- A micro-power neural spike detector and feature extractor in .13μm CMOSJeremy Holleman, Apurva Mishra, Chris Diorio, Brian P. Otis. 333-336 [doi]
- A compact and programmable high-frequency oscillator based on a MEMS resonatorFrederic Nabki, Faisal Ahmad, Karim Allidina, Mourad N. El-Gamal. 337-340 [doi]
- Characterization and design for variability and reliabilityKevin J. Nowka, Sani R. Nassif, Kanak Agarwal. 341-346 [doi]
- A 9Gbit/s serial transceiver for on-chip global signaling over lossy transmission linesJunyoung Park, Joshua Jaeyoung Kang, Sunghyun Park, Michael P. Flynn. 347-350 [doi]
- A 28mW OFDM baseband receiver chip for DVB-T/H with all digital synchronizationTing-Chen Wei, Wei-Chang Liu, Chi-Yao Tseng, Syu-Siang Long, Shyh-Jye Jou, Muh-Tian Shiue. 351-354 [doi]
- Nonvolatile Magnetic Flip-Flop for standby-power-free SoCsNoboru Sakimura, Tadahiko Sugibayashi, Ryusuke Nebashi, Naoki Kasai. 355-358 [doi]
- A fully integrated pulsed-LASER time-of-flight measurement system with 12ps single-shot precisionTino Copani, Bert Vermeire, Anuj Jain, Habib Karaki, Kailash Chandrashekar, Sushmit Goswami, Jennifer Kitchen, Hoon Hee Chung, Ilker Deligoz, Bertan Bakkaloglu, Hugh J. Barnaby, Sayfe Kiaei. 359-362 [doi]
- A low-power IC design for the wireless monitoring system of the orthopedic implantsHong Chen, Chen Jia, Yi Chen, Ming Liu, Chun Zhang, Zhihua Wang. 363-366 [doi]
- Tessellation-enabled shader for a bandwidth-limited 3D graphics engineKyusik Chung, Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim. 367-370 [doi]
- Lithography options for the 32nm half pitch node and beyondKurt Ronse, Philippe Jansen, Roel Gronheid, Eric Hendrickx, Mireille Maenhoudt, Mieke Goethals, Geert Vandenberghe. 371-378 [doi]
- 45nm high-k + metal gate strain-enhanced CMOS transistorsChris Auth. 379-386 [doi]
- Will BiCMOS stay competitive for mmW applications ?Patrice Garcia, Alain Chantre, Sebastien Pruvost, Pascal Chevalier, Sean T. Nicolson, David Roy, Sorin P. Voinigescu, Christophe Garnier. 387-394 [doi]
- Microelectronics for the real world: "Moore" versus "More than Moore"John P. Kent, Jagdish Prasad. 395-402 [doi]
- A 512-KB level-2 cache design in 45-nm for low power IA processor silverthorneMohammed H. Taufique, Alex Okpisz, Haseeb N. Ahmed, John R. Riley, Mohammad M. Hasan, Gianfranco Gerosa. 403-406 [doi]
- A voltage scalable 0.26V, 64kb 8T SRAM with Vmin lowering techniques and deep sleep modeTae-Hyoung Kim, Jason Liu, Chris H. Kim. 407-410 [doi]
- Compensation of systematic variations through optimal biasing of SRAM wordlinesAndrew Carlson, Zheng Guo, Liang-Teck Pang, Tsu-Jae King Liu, Borivoje Nikolic. 411-414 [doi]
- Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlinesUmut Arslan, Mark P. McCartney, Mudit Bhargava, Xin Li, Ken Mai, Lawrence T. Pileggi. 415-418 [doi]
- A 135mV 0.13μW process tolerant 6T subthreshold DTMOS SRAM in 90nm technologyMyeong-Eun Hwang, Kaushik Roy. 419-422 [doi]
- Robust ultra-low voltage ROM designMingoo Seok, Scott Hanson, Jae-sun Seo, Dennis Sylvester, David Blaauw. 423-426 [doi]
- A million cycle 0.13um 1Mb embedded SONOS Flash memory using Successive Approximated Read CalibrationNan Wang, Xiang Yao, Yu Lei, Guoyou Feng, Qiaohua Dong, Liang Xu, Lu Guo, Zi Wang, T. S. Tang. 427-430 [doi]
- A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOIAlexander Rylyakov, José A. Tierno, George English, Michael Sperling, Daniel J. Friedman. 431-434 [doi]
- Clocking circuits for a 16Gb/s memory interfaceTing Wu, Xudong Shi, Kambiz Kaviani, Haechang Lee, Jung-Hoon Chun, T. J. Chin, Jie Shen, Rich Perego, Ken Chang. 435-438 [doi]
- A 1V 15.6mW 1-2GHz -119dBc/Hz @ 200kHz clock multiplying DLLSander Gierkink. 439-442 [doi]
- A 0.5-to-2.5GHz supply-regulated PLL with noise sensitivity of -28dBAbhijith Arakali, Srikanth Gondi, Pavan Kumar Hanumolu. 443-446 [doi]
- 20 GHz low power QVCO and De-skew techniques in 0.13μm digital CMOSMasum Hossain, Anthony Chan Carusone. 447-450 [doi]
- A 3 GHz Spread Spectrum Clock Generator for SATA applications using chaotic PAM modulationFabio Pareschi, Gianluca Setti, Riccardo Rovatti. 451-454 [doi]
- A 1.5 GHz spread spectrum clock generator with a 5000ppm piecewise linear modulationMinyoung Song, Sunghoon Ahn, Inhwa Jung, Yongtae Kim, Chulwoo Kim. 455-458 [doi]
- A 8×5 Gb/s source-synchronous receiver with clock generator phase error correctionAnkur Agrawal, Pavan Kumar Hanumolu, Gu-Yeon Wei. 459-462 [doi]
- Millimeter-wave CMOS integrated circuits for gigabit WPAN applicationsTian-Wei Huang, Huei Wang. 463-470 [doi]
- A zero-IF 60GHz transceiver in 65nm CMOS with ≫ 3.5Gb/s linksAlexander Tomkins, Ricardo Andres Aroca, Takuji Yamamoto, Sean T. Nicolson, Yoshiyasu Doi, Sorin P. Voinigescu. 471-474 [doi]
- Low-cost fully integrated BiCMOS transceiver for pulsed 24-GHz automotive radar sensorsLaurence Moquillon, Patrice Garcia, Sebastien Pruvost, Stéphane Le Tual, Maxime Marchetti, Laurent Chabert, Nicole Bertholet, Angelo Scuderi, Salvatore Scaccianoce, Alberto Serratore, Nicolo Ivan Piazzese, Cedric Dehos, Dominique Morche. 475-478 [doi]
- A 0.13μm CMOS fully differential receiver with on-chip baluns for 60GHz broadband wireless communicationsChao-Shiun Wang, Juin-Wei Huang, Kun-Da Chu, Chorng-Kuang Wang. 479-482 [doi]
- A low power 20 GHz 1.5 Gb/s CMOS injection-pulling FSK modulator and frequency discriminator for 60GHz linksShon-Hang Wen, Chao-Shiun Wang, Chorng-Kuang Wang. 483-486 [doi]
- A 24/77GHz dual-band BiCMOS frequency synthesizerVipul Jain, Babak Javid, Payam Heydari. 487-490 [doi]
- An X/Ku-band frequency synthesizer using a 9-Bit quadrature DDSXuefeng Yu, Fa Foster Dai, Dayu Yang, J. David Irwin, Richard C. Jaeger. 491-494 [doi]
- A dynamic offset control technique for comparator design in scaled CMOS technologyXiaolei Zhu, Yanfei Chen, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Hirotaka Tamura, Sanroku Tsukamoto, Tadahiro Kuroda. 495-498 [doi]
- A low-voltage OP amp with digitally controlled algorithmic approximationDong-Woo Jee, Seung-Jin Park, Hong June Park, Jae-Yoon Sim. 499-502 [doi]
- 2 Audio ΣΔ modulator using chopper stabilization and fully randomized DWAYi-Gyeong Kim, Min Hyung Cho, Kwi-Dong Kim, Jong-Kee Kwon, Jongdae Kim. 503-506 [doi]
- An ultra low power 1V, 220nW temperature sensor for passive wireless applicationsYu-Shiang Lin, Dennis Sylvester, David Blaauw. 507-510 [doi]
- A 9-Bit configurable current source with enhanced output resistance for cochlear stimulatorsSong Guo, Hoi Lee, Philipos Loizou. 511-514 [doi]
- Super-resolution: Imaging beyond the pixel size limitTamer A. Elkhatib, Khaled N. Salama. 515-518 [doi]
- Polysilicon vertical actuator powered with waste heatJorge Varona, Margarita Tecpoyotl-Torres, Anas A. Hamoui. 519-522 [doi]
- Low noise μWatt interface circuits for wireless implantable real-time digital blood pressure monitoringPeng Cong, Wen H. Ko, Darrin J. Young. 523-526 [doi]
- A flexible decoder IC for WiMAX QC-LDPC codesTzu-Chieh Kuo, Alan N. Willson Jr.. 527-530 [doi]
- Minimizing the supply sensitivity of CMOS ring oscillator by jointly biasing the supply and control voltagePing-Hsuan Hsieh, Jay Maxey, Chih-Kong Ken Yang. 531-534 [doi]
- The Superchip: Innovative teaching of IC design and manufacturePeter R. Wilson, Reuben Wilcock, Iain McNally, Matthew Swabey, Bashir M. Al-Hashimi. 535-538 [doi]
- A 3D graphics processor with fast 4D vector inner product units and power aware texture cacheJae-Sung Yoon, Donghyun Kim, Chang-Hyo Yu, Lee-Sup Kim. 539-542 [doi]
- Timing yield enhancement through soft edge flip-flop based designMichael Wieckowski, Young-Min Park, Carlos Tokunaga, Dong Woon Kim, Zhiyoong Foo, Dennis Sylvester, David Blaauw. 543-546 [doi]
- 1/5 power reduction by global optimization based on fine-grained body biasingYasumi Nakamura, David Levacq, Limin Xiao, Takuya Minakawa, Taro Niiyama, Makoto Takamiya, Takayasu Sakurai. 547-550 [doi]
- A DC-DC converter with a dual VCDL-based ADC and a self-calibrated DLL-based clock generator for an energy-aware EISC processorSunghwa Ok, Jungmoon Kim, Gilwon Yoon, Hyunho Chu, Jaegeun Oh, Seon Wook Kim, Chulwoo Kim. 551-554 [doi]
- Active autonomous AC-DC converter for Piezoelectric Energy Scavenging SystemsEnrico Dallago, Daniele Miatton, Giuseppe Venchi, Valeria Bottarel, Giovanni Frattini, Giulio Ricotti, Monica Schipani. 555-558 [doi]
- A 10Gb/s receiver with linear backplane equalization and mixer-based self-aligned CDRSimone Erba, Massimo Pozzoni, Matteo Pisati, Riccardo Brama, Davide Sanzogni, Emanuele Depaoli, Paolo Viola, Francesco Svelto. 559-562 [doi]
- A 12.5-Gbps, 7-bit transmit DAC with 4-tap LUT-based equalization in 0.13μm CMOSHayun Chung, Andrew Liu, Gu-Yeon Wei. 563-566 [doi]
- Active deskew in injection-locked clockingLin Zhang, Berkehan Ciftcioglu, Hui Wu. 567-570 [doi]
- A 53 GHz DCO for mm-wave WPANRaffaella Genesi, Francesco M. De Paola, Danilo Manstretta. 571-574 [doi]
- Twisted inductors for low coupling mixed-signal and RF applicationsNathan M. Neihart, David J. Allstot, Matt Miller, Pat Rakers. 575-578 [doi]
- A common-base linear rf power amplifier for 3G cellular applicationsFlavio Avanzo, Francesco M. De Paola, Danilo Manstretta. 579-582 [doi]
- Design of low power CMOS ultra-wideband 3.1-10.6 GHz pulse-based transmittersKuan-Yu Lin, Mourad N. El-Gamal. 583-586 [doi]
- Energy-efficient wireless front-end concepts for ultra lower power radioJohn R. Long, Wanghua Wu, Yunzhi Dong, Yi Zhao, Mihai A. T. Sanduleanu, John F. M. Gerrits, Gerrit van Veenendaal. 587-590 [doi]
- A 0.4 nJ/b 900MHz CMOS BFSK super-regenerative receiverJames Ayers, Kartikeya Mayaram, Terri S. Fiez. 591-594 [doi]
- A 900-MHz low-power transmitter with fast frequency calibration for wireless sensor networksNapong Panitantum, Kartikeya Mayaram, Terri S. Fiez. 595-598 [doi]
- A 3.5-mW 15-Mbps O-QPSK transmitter for real-time wireless medical imaging applicationsYao-Hong Liu, Tsung-Hsien Lin. 599-602 [doi]
- A CMOS direct conversion transmitter with integrated in-band harmonic suppression for IEEE 802.22 cognitive radio applicationsJongsik Kim, Seungsoo Kim, Jaewook Shin, Youngcho Kim, Junki Min, Kihong Kim, Hyunchol Shin. 603-606 [doi]
- A 5-GHz wireless LAN transmitter with integrated tunable high-Q RF filterRobert F. Wiser, Masoud Zargari, David K. Su, Bruce A. Wooley. 607-610 [doi]
- A 6.5 Gb/s backplane transmitter with 6-tap FIR equalizer and variable tap spacingMike Bichan, Anthony Chan Carusone. 611-614 [doi]
- Phase-locking in wireline systems: Present and futureBehzad Razavi. 615-622 [doi]
- A 20Gb/s SerDes transmitter with adjustable source impedance and 4-tap feed-forward equalization in 65nm bulk CMOSRick A. Philpott, James S. Humble, Robert A. Kertis, Karl E. Fritz, Barry K. Gilbert, Erik S. Daniel. 623-626 [doi]
- Wideband mmWave CML static divider in 65nm SOI CMOS technologyDaeik D. Kim, Choongyeun Cho, Jonghae Kim, Jean-Olivier Plouchart. 627-634 [doi]
- A 32/16 Gb/s 4/2-PAM transmitter with PWM pre-Emphasis and 1.2 Vpp per side output swing in 0.13-μm CMOSHorace Cheng, Anthony Chan Carusone. 635-638 [doi]
- A 5-Gb/s/pin transceiver for DDR memory interface with a crosstalk suppression schemeKwang-Il Oh, Lee-Sup Kim, Kwang-Il Park, Young-Hyun Jun, Kinam Kim. 639-642 [doi]
- EMI resisting smart-power integrated LIN driver with reduced slope pumpingJean-Michel Redoute, Michiel Steyaert. 643-646 [doi]
- Stacking technology based on 8-inch wafers using direct connection between TSV and micro-bumpNobuaki Miyakawa, Eiri Hashimoto, Takanori Maebashi, Natsuo Nakamura, Yutaka Sacho, Shigeto Nakayama, Shinjiro Toyoda. 647-650 [doi]
- Clock distribution networks for 3-D ictegrated CircuitsVasilis F. Pavlidis, Ioannis Savidis, Eby G. Friedman. 651-654 [doi]
- Inter-die signaling in three dimensional integrated circuitsChristopher Mineo, Ravi Jenkal, Samson Melamed, W. Rhett Davis. 655-658 [doi]
- Variability in 3-D integrated circuitsFilipp Akopyan, Carlos Tadeo Ortega Otero, David Fang, Sandra J. Jackson, Rajit Manohar. 659-662 [doi]
- 3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementationMuhannad S. Bakir, Calvin King, Deepak C. Sekar, Hiren D. Thacker, Bing Dang, Gang Huang, Azad Naeemi, James D. Meindl. 663-670 [doi]
- SiP for GSM/EDGE in CMOS technologyGiuseppe Li Puma, Ernst Kristan, Paolo De Nicola, Cyril Vannier, Braam Greyling, Salvatore Piccolella. 671-674 [doi]
- Heterogeneous multicore SoC for secure multimedia applicationsHiroyuki Kondo, Masami Nakajima, Sugako Otani, Osamu Yamamoto, Norio Masui, Naoto Okumura, Mamoru Sakugawa, Masaya Kitao, Koichi Ishimi, Masayuki Sato, Fumitaka Fukuzawa, Kazuhiro Inaoka, Yoshihiro Saito, Kazutami Arimoto, Toru Shimizu. 675-678 [doi]
- A 159.2mW SoC implementation of T-DMB receiver including stacked memoriesJoohyun Lee, Sungdo Kim, Jinkyu Kim, Duckhwan Kim, Young-Su Kwon, Minseok Choi, Kihyuk Park, Bontae Koo, Nak-Woong Eum, Hyuckjae Lee. 679-682 [doi]
- Modeling, measurement and mitigation of crosstalk noise coupling in 3D-ICsLiuchun Cai, Ramesh Harjani. 683-686 [doi]
- A method using circuit/substrate macro modeling to analyze substrate noise in a 3.2-GHz 350M-transistor microprocessorMikiko Sode Tanaka, Mikihiro Kajita, Naoya Nakayama, Satoshi Nakamoto. 687-690 [doi]
- Characterization of random decision errors in clocked comparatorsBrian S. Leibowitz, Jaeha Kim, Jihong Ren, Chris J. Madden. 691-694 [doi]
- Noise tolerant oscillator design using perturbation projection vector analysisIgor Vytyaz, Josh Carnes, Ting Wu, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram. 695-698 [doi]
- Strong injection locking of low-Q LC oscillatorsMozhgan Mansuri, Frank O'Mahony, Ganesh Balamurugan, James E. Jaussi, Joseph T. Kennedy, Sudip Shekhar, Randy Mooney, Bryan Casper. 699-702 [doi]
- A low power 1.3GHz dual-path current mode Gm-C filterManisha Gambhir, Vijay Dhanasekaran, José Silva-Martínez, Edgar Sánchez-Sinencio. 703-706 [doi]
- A 1V downconversion filter using duty-cycle controlled bandwidth tuningPeter Kurahashi, Pavan Kumar Hanumolu, Un-Ku Moon. 707-710 [doi]
- A reconfigurable FIR filter embedded in a 9b successive approximation ADCJoshua Jaeyoung Kang, David T. Lin, Li Li, Michael P. Flynn. 711-714 [doi]
- Voltage references for ultra-low supply voltagesPeter R. Kinget, Christos Vezyrtzis, Ed Chiang, B. Hung, T. L. Li. 715-720 [doi]
- Design of bandgap voltage reference circuit with all TFT devices on glass substrate in a 3-μm LTPS processTing-Chou Lu, Ming-Dou Ker, Hsiao Wen Zan, Chun-Hung Kuo, Chun-Huai Li, Yao-Jen Hsieh, Chun-Ting Liu. 721-724 [doi]
- Deep submicron effects on data converter building blocksWilliam P. Evans, David Burnell. 725-728 [doi]
- A highly linear SAW-less CMOS receiver using a mixer with embedded Tx filtering for CDMANamsoo Kim, Lawrence E. Larson, Vladimir Aparin. 729-732 [doi]
- High-power digital envelope modulator for a polar transmitter in 65nm CMOSManel Collados, Paul T. M. van Zeijl, Nenad Pavlovic. 733-736 [doi]
- A 2.4GHz, 20dBm class-D PA with single-bit digital polar modulation in 90nm CMOSJason T. Stauth, Seth R. Sanders. 737-740 [doi]
- Linearity and efficiency enhancement strategies for 4G wireless power amplifier designsLarry Larson, Donald Kimball, Peter M. Asbeck. 741-748 [doi]
- An analog enhanced all digtial RF fractional-N PLL with self-calibrated capabilityPing-Ying Wang, Jing-Hong Conan Zhan, Hsiang-Hui Chang, Bing-Yu Hsieh. 749-752 [doi]
- A ΔΣ fractional-N synthesizer with customized noise shaping for WCDMA/HSDPA applicationsXueyi Yu, Yuanfeng Sun, Woogeun Rhee, Zhihua Wang, Hyung Ki Ahn, Byeong-ha Park. 753-756 [doi]