Richard C. Jaeger - researchr alias

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Viewing Publication 1 - 30 from 30

2018

First and Second Order Piezoresistive Characteristics of CMOS FETs: Weak through Strong InversionRichard C. Jaeger, Jeffrey C. Suhling. essderc 2018: 126-129 [doi]

2014

2011

An X- and Ku-Band Wideband Recursive Receiver MMIC With Gain-ReuseDesheng Ma, Fa Foster Dai, Richard C. Jaeger, J. David Irwin. jssc, 46(3):562-571, 2011. [doi]

2010

2009

Delta-Sigma Modulation for Direct Digital Frequency SynthesisDayu Yang, Foster F. Dai, Weining Ni, Yin Shi, Richard C. Jaeger. tvlsi, 17(6):793-802, 2009. [doi]

2008

An 11-bit 8.6GHz direct digital synthesizer MMIC with 10-bit segmented nonlinear DACXueyang Geng, Xuefeng Yu, Fa Foster Dai, J. David Irwin, Richard C. Jaeger. esscirc 2008: 362-365 [doi]

A fully integrated zero-IF mobile TV tuner RFIC for S-band CMMB applicationYin Shi, Fa Foster Dai, Jun Yan, Hua Xu, Xuelian Zhang, Heping Ma, Fang Yuan, Xin Guan, Richard C. Jaeger. cicc 2008: 253-256 [doi]

A multifunction transceiver RFIC for 802.11a/b/g WLAN and DVB-H applicationsYin Shi, Foster F. Dai, Jun Yan, Xueqing Hu, Hua Xu, Ming Gu, Xuelian Zhang, Qiming Xu, Bei Chen, Fangxiong Chen, Peng Yu, Heping Ma, Fang Yuan, Richard C. Jaeger. cicc 2008: 249-252 [doi]

A 12-Bit Cryogenic and Radiation-Tolerant Digital-to-Analog Converter for Aerospace Extreme Environment ApplicationsYuan Yao, Foster F. Dai, Richard C. Jaeger, John D. Cressler. tie, 55(7):2810-2819, 2008. [doi]

A 12 GHz 1.9 W Direct Digital Synthesizer MMIC Implemented in 0.18 µm SiGe BiCMOS TechnologyXuefeng Yu, Fa Foster Dai, J. David Irwin, Richard C. Jaeger. jssc, 43(6):1384-1393, 2008. [doi]

An X/Ku-band frequency synthesizer using a 9-Bit quadrature DDSXuefeng Yu, Fa Foster Dai, Dayu Yang, J. David Irwin, Richard C. Jaeger. cicc 2008: 491-494 [doi]

2006

2005

An high speed integrated equalizer for dispersion compensation in 10Gb/s fiber networksVasanth Kakani, Foster F. Dai, Richard C. Jaeger. iscas 2005: 1178-1181 [doi]

2004

A novel DDS architecture using nonlinear ROM addressing with improved compression ratio and quantisation noiseMalinky Ghosh, Lakshmi S. J. Chimakurthy, Foster F. Dai, Richard C. Jaeger. iscas 2004: 705-708

Delay analysis and optimal biasing for high speed low power Current Mode Logic circuitsVasanth Kakani, Foster F. Dai, Richard C. Jaeger. iscas 2004: 869-872

2000

CMOS stress sensors on [100] siliconRichard C. Jaeger, Jeffrey C. Suhling, Ramanathan Ramani, Arthur T. Bradley, Jianping Xu. jssc, 35(1):85-95, 2000. [doi]

1999

Test chips for die stress characterization using arrays of CMOS sensorsArthur T. Bradley, Richard C. Jaeger, Jeffrey C. Suhling, Y. Zou. cicc 1999: 147-150 [doi]

Neuro-fuzzy architecture for CMOS implementationBogdan M. Wilamowski, Richard C. Jaeger, M. Okay Kaynak. tie, 46(6):1132-1136, 1999. [doi]

1996

Implementation of RBF type networks by MLP networksBogdan M. Wilamowski, Richard C. Jaeger. icnn 1996: 1670-1675 [doi]

CMOS implementation of a pulse-coupled neuron cellBogdan M. Wilamowski, Richard C. Jaeger, Mary Lou Padgett, Lawrence J. Myers. icnn 1996: 986-990 [doi]

1992

A high-speed sensing scheme for 1T dynamic RAMs utilizing the clamped bit-line sense amplifierTravis N. Blalock, Richard C. Jaeger. jssc, 27(4):618-625, April 1992. [doi]

1991

A high-speed clamped bit-line current-mode sense amplifierTravis N. Blalock, Richard C. Jaeger. jssc, 26(4):542-548, April 1991. [doi]

1986

Computer-Aided Design of One-Dimensional MOSFET Impurity ProfilesRichard C. Jaeger. tcad, 5(1):198-203, 1986. [doi]

1983

An Efficient Numerical Algorithm for Simulation of MOS CapacitanceRichard C. Jaeger, Fritz H. Gaensslen, Sherra E. Diehl. tcad, 2(2):111-116, 1983. [doi]

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Publications by 'Richard C. Jaeger'

Viewing Publication 1 - 30 from 30

2018

2014

2011

2010

2009

2008

2006

2005

2004

2000

1999

1996

1992

1991

1986

1983

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