Table of Contents

• Smart Connected Sensors - Enablers for the IoTUdo Gomez. 1 [doi]
• Unleashing Technology Solutions for a New Era of Connected IntelligenceGary L. Patton. 2 [doi]
• Autonomous Vehicles SEnsor NeedsBaher Haroun. 3 [doi]
• "In-memory Computing": Accelerating AI ApplicationsEvangelos Eleftheriou. 4-5 [doi]
• MOS Device Technology using Alternative Channel Materials for Low Power Logic LSIShinichi Takagi, Kimihiko Kato Wu-Kang Kim, Kwangwon Jo, Ryo Matsumura, Ryotaro Takaguchi, Dae-Hwan Ahn, Takahiro Gotow, Mitsuru Takenaka. 6-11 [doi]
• Si MOS technology for spin-based quantum computingL. Hutin, B. Bertrand, R. Maurand, A. Crippa, M. Urdampilleta, Y.-J. Kim, A. Amisse, H. Bohuslavskyi, L. Bourdet, Sylvain Barraud, X. Jeh, Yann-Michel Niquet, Marc Sanquer, C. Bauerle, T. Meunier, S. De Franceschi, Maud Vinet. 12-17 [doi]
• Charge Injection in Normally-Off p-GaN Gate AlGaN/GaN-on-Si HFETsLuca Savadi, Giuseppe Iannaccone, Sebastien Sicre, Simone Lavanza, Gianluca Fiori, Oliver Haeberlen, Gilberto Curatola. 18-21 [doi]
• Localization and analysis of surface charges trapped in AlGaN/GaN HEMTs using multiple secondary MIS gatesL. Heuken, Muhammad Alshahed, A. Ottaviani, M. Alomari, Joachim N. Burghartz, U. Waizmann, T. Reindl. 22-25 [doi]
• Verification of the Injection Enhancement Effect in IGBTs by Measuring the Electron and Hole Currents SeparatelyT. Hoshii, K. Furukawa, Kuniyuki Kakushima, M. Watanabe, N. Shigvo, Takuya Saraya, T. Takakura, K. Itou, M. Fukui, S. Suzuki, K. Takeuchi, I. Muneta, Hitoshi Wakabayashi, Shinichi Nishizawa, Kazuo Tsutsui, Toshiro Hiramoto, H. Ohashi, H. Lwai. 26-29 [doi]
• High Mobility 4H-SiC MOSFET Using a Thin SiO2/Al2O3 Gate StackF. Arith, J. Urrcsti, K. Vasilevskiy, S. Oisenl, N. Wright, A. O'Neill. 30-33 [doi]
• Effect of Electron-phonon Scattering on the Thermal Conductivity of Si NanowiresKantawong Vuttivorakulchai, Mathieu Luisier, Andreas Schenk. 34-37 [doi]
• First-principles study of electron transport through phase-engineered Au - Mo Te2contactsM. E. Lee, U. G. Vej-Hansen, Petr A. Khomyakov, D. Stradi, J. Wellendorff, S. Smidstrup, Kurt Stokbro. 38-41 [doi]
• High performance WTe2-MoS2in-plane heterojunction Tunnel Field Effect TransistorsJean Choukroun, Marco Pala, Shiang Fang, Efthimios Kaxiras, Philippe Dollfus. 42-45 [doi]
• Observation and Analysis of Bit-by-Bit Cell Current Variation During Data-Retention of TaOx-based ReRAMKazuki Maeda, Shinpei Matsuda, Ken Takeuchi, Ryutaro Yasuhara. 46-49 [doi]
• Energy-Efficient Logic-in-Memory I-bit Full Adder Enabled by a Physics-Based RRAM Compact ModelFrancesco Maria Puglisi, Lorenzo Pacchioni, Nicolo Zagni, Paolo Pavan. 50-53 [doi]
• A Physically Unclonable Function with BER < 0.35% for Secure Chip Authentication Using Write Speed Variation of RRAMJianguo Yang, Xing Li, Tao Wang, Xiaoyong Xue, Zhiliang Hong, Yuanyuan Wang, David Wei Zhang, Hongliang Lu. 54-57 [doi]
• Towards Automotive Grade Embedded RRAMJ. R. Jameson, J. Dinh, N. Gonzales, S. Hollmer, S. Hsu, D. Kim, F. Koushan, D. Lewis, E. Runnion, J. Shields, A. Tysdal, D. Wang, V. Gopinath. 58-61 [doi]
• Analytic variability study of inference accuracy in RRAM arrays with a binary tree winner-take-all circuit for neuromorphic applicationsJonas Doevenspeck, Robin Degraeve, Stefan Cosemans, Philippe Roussel, Bram-Ernst Verhoef, Rudy Lauwereins, Wim Dehaene. 62-65 [doi]
• Monolithically integrated 1 TFT-1RRAM non-volatile memory cells fabricated on PI flexible substrateA. Lebanov, Andrea Fantini, Robin Degraeve, Manoj Nag, Myriam Willegems, Steve Smout, Soeren Steudel, Jan Genoe, P. Horemans, K. Mvnv. 66-69 [doi]
• A Large-Area Gravure Printed Process for P-type Organic Thin-Film Transistors on Plastic SubstratesM. Charbonneau, D. Locatelli, S. Lombard, Christophe Serbutoviez, L. Tournon, Fabrizio Torricelli, Sahel Abdinia, Eugenio Cantatore, M. Fattori. 70-73 [doi]
• 2-FET for fast logic applicationsK. H. Lee, H. El Dirani, Pascal Fonteneau, Maryline Bawedin, S. Sato, Sorin Cristoloveanu. 74-77 [doi]
• Novel Back Gate Doping Ultra Low Retention Power 22nm FDSOl SRAM for IOT ApplicationMingcheng Chang, Nigel Chan, Vivek Joshi, Sandra Hecker, Udo Ziller, Petra Poth, Alban Zaka, Tom Herrmann, Seunghwan Seo, Hongsik Yoon, Xin Zou, Zhen Xu, Hema Ramamurthy, Torsten Klick, Gabriele Congedo, Youmean Lee, Elke Erben, Gerd Zschaetzsch, Juergen Faul, Jon Kluth, Joerg Schmid, Ralf Van Bentum, Chad Weintraub. 78-81 [doi]
• Integration of SPAD in 28nm FDSOI CMOS technologyT. Chaves de Albuquerque, Francis Calmon, Raphael Clerc, Patrick Pittet, Y. Benhammou, Dominique Golanski, S. Jouan, D. Rideau, Andreia Cathelin. 82-85 [doi]
• BJT Device and Circuit Co-Optimization Enabling Bandgap Reference and Temperature Sensing in 7-nm FinFETUmanath Kamath, Tao Yu, Wei Yao, Edward Cullen, John Jennings, Susan Wu, Peng Lim, Brendan Farley, Robert Bogdan Staszewski. 86-89 [doi]
• OLED-on-Silicon Microdisplays: Technology, Devices, ApplicationsUwe Vogel, Philipp Wartenberg, Bernd Richter, Stephan Brenner, Karsten Fehse, Matthias Schober. 90-93 [doi]
• Low-Noise Single Photon Avalanche Diodes in a 110nm CIS TechnologyManuel Moreno Garcia, Hesong Xu, Leonardo Gasparini, Matteo Perenzoni. 94-97 [doi]
• Low Temperature and Radiation Stability of Flexible IGZO TFTs and their Suitability for Space ApplicationsJulio C. Costa, Arash Pouryazdan, Julianna Panidi, Thomas Anthopoulos, Maciej O. Liedke, Christof Schneider, Andreas Wagner, Niko Münzenrieder. 98-101 [doi]
• Low Profile Open MEMS and ASIC Packages manufactured by Flexible Hybrid Integration in a Roll-to-Roll compatible processIndranil Bose, Nagarajan Palavesam, Christian Hochreiter, Christof Landesberger, Christoph Kutter. 102-106 [doi]
• Integrated Graphene Photonic Devices: Status and ChallengesDaniel Schall 0003. 107-109 [doi]
• Electric Double Layer Esaki Tunnel Junction in a 40-nm-Length, WSe2 Channel Grown by Molecular Beam Epitaxy on Al203Paolo Paletti, Alan C. Seabaugh, Ruoyu Yue, Christopher L. Hinkle. 110-113 [doi]
• Double gate n-type WSe2 FETs with high-k top gate dielectric and enhanced electrostatic controlNicolo Oliva, Emanuele A. Casu, Matteo Cavalieri, Adrian M. Ionescu. 114-117 [doi]
• Gated Four-Probe Method to Evaluate the Impact of SAM Gate Dielectric on Mobility in MoS2 FETTakamasa Kawanago, Tomoaki Oba, Ryo Ikoma, Hiroyuki Takagi, Shunri Oda. 118-121 [doi]
• Towards IC-based quantum sensing - recent achievements and future research trendsJ. Anders, T. Pfau, J. Wrachtrup, Martin B. Plenio, Fedor Jelezko, Klaus Lips. 122-125 [doi]
• First and Second Order Piezoresistive Characteristics of CMOS FETs: Weak through Strong InversionRichard C. Jaeger, Jeffrey C. Suhling. 126-129 [doi]
• CMOS Compatible Pyroelectric Applications Enabled by Doped HfO2 Films on Deep-Trench StructuresC. Mart, Wenke Weinreich, M. Czernohorsky, Stefan Riedel, S. Zybell, K. Kuhnel. 130-133 [doi]
• Temperature monitoring of short-gate length AlGaN/GaN HEMT via an integrated sensorFlavien Cozette, Marie Lesecq, Nicolas Defrance, Michel Rousseau, Jean-Claude de Jaeger, Adrien Cutivet, Hassan Maher. 134-137 [doi]
• Emerging Non-Volatile Memory and Thin-Film Transistor Technologies for Future 3D-LSIMasumi Saitoh, Shosuke Fujii, Minoru Oda, Marina Yamaguchi, Shoichi Kabuyanagi, Yoko Yoshimura, Kensuke Ota, Kiwamu Sakuma, Yuuichi Kamimuta. 138-141 [doi]
• Ferroelectric Tunnel Junctions based on Ferroelectric-Dielectric Hf0.5Zr0.5.O2/ A12O3Capacitor StacksBenjamin Max, Michael Hoffmann, Stefan Slesazeck, Thomas Mikolajick. 142-145 [doi]
• Study of breakdown in STT-MRAM using ramped voltage stress and all-in-one maximum likelihood fitSimon Van Beek, Philippe Roussel, Barry O'Sullivan, Robin Degraeve, Stefan Cosemans, Dimitri Linten, Gouri Sankar Kar. 146-149 [doi]
• Endurance-based Dynamic VTHDistribution Shaping of 3D-TLC NAND Flash Memories to Suppress Both Lateral Charge Migration and Vertical Charge De-trap and Increase Data-retention Time by 2.7xShun Suzuki, Yoshiaki Deguchi, Toshiki Nakamura, Ken Takeuchi. 150-153 [doi]
• RF FDSOI Technology and modellingDavid L. Harame. 154 [doi]
• FD-SOI integration solutions for analog, RF and Millimeter-wave applicationsAndreia Cathelin. 155 [doi]
• FDSOI circuit design for high energy efficiency: Wide operating range and ULP applications - a 7-year experienceEdith Beigné. 156 [doi]
• Exploiting FDSOI towards minimum energy point operation in processors and machine learning acceleratorsMarian Verhelst. 157 [doi]
• Scaling CMOS beyond Si FinFET: an analog/RF perspectiveBertrand Parvais, Geert Hellings, Marco Simicic, Pieter Weckx, Jérôme Mitard, Doyoung Jang, V. Deshpande, B. van Liempc, A. Veloso, A. Vandooren, N. Waldron, Piet Wambacq, Nadine Collaert, Diederik Verkest. 158-161 [doi]
• InGaAs FinFETs 3D Sequentially Integrated on FDSOI Si CMOS with Record PerfomanceC. Convertino, C. B. Zota, Daniele Caimi, Marilyne Sousa, L. Czornomaz. 162-165 [doi]
• Static and Low Frequency Noise Characterization of InGaAs MOSFETs and FinFETs on InsulatorT. A. Karatsori, K. Bennamane, Christoforos G. Theodorou, L. Czornomaz, Jean Fompeyrine, C. B. Zota, C. Convcrtino, G. Ghibaudo. 166-169 [doi]
• Why SPICE Is Just As Good And Just As Bad For IC Design As It Was 40 Years AgoLaurence W. Nagel, Colin C. McAndrew. 170-173 [doi]
• Compact MEMS modeling to design full adder in Capacitive Adiabatic LogicAyrat Galisultanov, Yann Perrin, Hervé Fanet, Louis Hutin, Gaël Pillonnet. 174-177 [doi]
• Prediction of SRAM Reliability Under Mechanical Stress Induced by Harsh En§ironmentsJ. Warmuth, Kay-Uwe Giering, André Lange, André Clausner, S. Schlipf, G. Kurz, M. Otto, J. Paul, Roland Jancke, A. Aal, Martin Gall, Ehrenfried Zschech. 178-181 [doi]
• Energy-Efficient Design in FDSOIBorivoje Nikolic. 182 [doi]
• mmWand high speed solutions enabled by FD-SOISorin P. Voinigescu. 183 [doi]
• Circuit Design Challenges of Highly-Integrated mm-Wave Radar-Based Sensors in SOI based TechnologiesVadim Issakov. 184 [doi]
• FD-SOI enabled mmWave telecommunication applications and system architecturesAnirban Bandyopadhyay. 185 [doi]
• Experimental extraction of BEOL composite equivalent thermal conductivities for application in self-heating simulationsErik Bury, Ben Kaczer, Simon Van Beek, D. Lintern. 186-189 [doi]
• Evolution and Optimization of BEOL MOM Capacitors Across Advanced CMOS NodesJinglin Shi, A. Sidelnicov, Kok Wai J. Chew, Mei See Chin, C. Schippel, J. M. M. dos Santos, F. Schlaphof, Lutz Meinshausen, John R. Long, David L. Harame. 190-193 [doi]
• ESD diodes with Si/SiGe superlattice I/O finFET architecture in a vertically stacked horizontal nanowire technologyMarco Simicic, Geert Hellings, Shih-Hung Chen, Naoto Horiguchi, Dimitri Linten. 194-197 [doi]
• Device modeling of solution-processed organic solar cells, photodiodes and photo-resistances Invited paperRaphael Clerc, Jérôme Vaillant, Lionel Hirsch. 198-201 [doi]
• Cell Designer - a Comprehensive TCAD-Based Framework for DTCO of Standard Logic CellsZoran Stanojevic, G. Strof, Franz Schanovsky, K. Steiner, O. Baumgartner, Ch. Kernstock, Markus Karner. 202-205 [doi]
• Gate Driver Solutions for Modern Power Devices and TopologiesReinhard Herzer. 206-214 [doi]
• HV Floating Switch Matrix with Parachute Safety Driving for 3D Echography SystemsGiulio Ricotti, Valeria Bottarel. 215-217 [doi]
• Fast acquisition of activation energy maps using temperature ramps for lifetime modeling of BTIK. Puschkarsky, Hans Reisinger, Christian Schlünder, Wolfgang Gustin, Tibor Grasser. 218-221 [doi]
• 3D TCAD modeling of NO2CNT FET sensorsStefania Carapezzi, Sebastian Eberle, Susanna Reggiani, Elena Gnani, Cosmin Roman, Christofer Hierold, Antonio Gnudi. 222-225 [doi]
• Performance Evaluation of Silicon Based Thermoelectric Generators Interest of Coupling Low Thermal Conductivity Thin Films and a Planar ArchitectureThierno-Moussa Bah, Stanjen Didenko, Stephane Monfray, Thomas Skotnicki, Emmanuel Dubois, Jean-Francois Robillard. 226-229 [doi]
• Random Dopant Fluctuation and Random Telegraph Noise in Nanowire and Macaroni MOSFETsAlessandro S. Spinelli, Christian Monzio Compagnoni, Andrea L. Lacaita. 230-233 [doi]
• Compact Modeling for Power Efficient Circuit DesignMitiko Miura-Mattausch, Hideyuki Kikuchihara, T. Kajiwara, Yuta Tanimoto, Atsushi Saito, Takahiro Iizuka, D. Navarro, Hans Jürgen Mattausch. 234-237 [doi]
• A Compact Model for Static and Dynamic Operation of Symmetric Double-Gate Junction FETsNikolaos Makris, Matthias Bucher, Farzan Jazaeri, Jean-Michel Sallese. 238-241 [doi]
• Analysis of Gate Current Wafer Level Variability in Advanced FD-SOI MOSFETsKrishna Pradeep, T. A. Karatsori, Thierry Poiroux, Andre Juge, Patrick Scheer, G. Gouget, E. Josse, G. Ghibando. 242-245 [doi]
• Characterization and Model Validation of Mismatch in Nanometer CMOS at Cryogenic TemperaturesP. A. 't Hart, Jeroen P. G. van Dijk, Masoud Babaie, Edoardo Charbon, A. Vladimircscu, Fabio Sebastiano. 246-249 [doi]
• Novel IC Sub-Threshold IDDQ Signature And Its Relationship To Aging During High Voltage StressFranco Stellari, Naigang Wang, Peilin Song. 250-253 [doi]
• RTN and LFN Noise Performance in Advanced FDSOI TechnologyL. Pirro, O. Zimmerhackl, A. Zaka, L. Miiller-Meskamp, R. Nelluri, T. Hermann, I. Cortes-Mayol, A. Huschka, M. Otto, E. Nowak, A. Mittal, Jan Hoentschel. 254-257 [doi]
• Current gain and low-frequency noise of symmetric lateral bipolar junction transistors on SOIQitao Hu, Xi Chen, Hans Norstrom, Shuangshuang Zeng, YiFei Liu, Fredrik Gustavsson, Shi-Li Zhang, Si Chen, Zhen Zhang. 258-261 [doi]