Analysis of Gate Current Wafer Level Variability in Advanced FD-SOI MOSFETs

Krishna Pradeep, T. A. Karatsori, Thierry Poiroux, Andre Juge, Patrick Scheer, G. Gouget, E. Josse, G. Ghibando. Analysis of Gate Current Wafer Level Variability in Advanced FD-SOI MOSFETs. In 48th European Solid-State Device Research Conference, ESSDERC 2018, Dresden, Germany, September 3-6, 2018. pages 242-245, IEEE, 2018. [doi]

Abstract

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