Abstract is missing.
- Low-Voltage Universal Cell (LVUC): A Compact Analog/Digital Logic Block for Mixed Signal FPGAsLalitha Mohana Kalyani-Garimella, Annajirao Garimella, Jaime Ramírez-Angulo, Ramón González Carvajal, Antonio J. López-Martín. 1-4 [doi]
- A Large-Scale Reconfigurable Analog Signal Processor (RASP) ICChristopher M. Twigg, Paul E. Hasler. 5-8 [doi]
- Determination of Power Gating Granularity for FPGA FabricArifur Rahman, Satyaki Das, Tim Tuan, Steven Trimberger. 9-12 [doi]
- Reconfigurable Asynchronous LogicRajit Manohar. 13-20 [doi]
- A 50-GHz Phase-Locked Loop in 130-nm CMOSChanghua Cao, Yanping Ding, K. O. Kenneth. 21-24 [doi]
- Common Gate Transformer Feedback LNA in a High IIP3 Current Mode RF CMOS Front-EndAntonio Liscidini, Cesare Ghezzi, Emanuele Depaoli, Guido Albasini, Ivan Bietti, Rinaldo Castello. 25-28 [doi]
- Passive & Active Control of Regenerative Standing & Soliton WavesWilliam F. Andress, David S. Ricketts, Xiaofeng Li, Donhee Ham. 29-36 [doi]
- A 0.9-V Double-Balanced Quadrature-Input Quadrature-Output Frequency DividerHui Zheng, Howard C. Luong. 37-40 [doi]
- Incremental Delta-Sigma Structures for DC Measurement: an OverviewJános Márkus, Philippe Deval, Vincent Quiquempoix, José B. Silva, Gabor C. Temes. 41-48 [doi]
- A 14mW 2.5MS/s 14bit Sigma-Delta Modulator Using Pseudo-Differential Split-Path Cascode AmplifiersZhiheng Cao, Tongyu Song, Shouli Yan. 49-52 [doi]
- A 100-MS/s 4-MHz Bandwidth 77.3-dB SNDR ΔΣ ADC with a Triple Sampling TechniqueYusuke Kanazawa, Yoshihisa Fujimoto, Pascal Lo Ré, Michael M. Miyamoto. 53-56 [doi]
- A 2.7mW 2MHz Continuous-Time ΣΔ Modulator with a Hybrid Active-Passive Loop FilterTongyu Song, Zhiheng Cao, Shouli Yan. 57-60 [doi]
- A 70-GHz Effective Sampling Rate On-Chip Oscilloscope with Time-Domain DigitizationMona Safi-Harb, Gordon W. Roberts. 61-64 [doi]
- Jitter And Signaling Test For High-Speed LinksMike Peng Li. 65-72 [doi]
- A Technique for Accurate Frequency Response Measurement of Integrated Continuous-Time FiltersShanthi Pavan, Tonse Laxminidhi. 77-80 [doi]
- Software Assisted Digital RF Processor for Single-Chip GSM Radio in 90 nm CMOSRobert Bogdan Staszewski, Tom Jung, Roman Staszewski, Khurram Muhammad, Dirk Leipold, Thomas Murphy, S. Sabin, John L. Wallberg, S. Larson, Mitch Entezari, J. Fresquez, S. Dondershine, S. Syed. 81-84 [doi]
- A Highly Integrated Power Management IC for Advanced Mobile ApplicationsChunlei Shi, Brett C. Walker, Eric Zeisel, Brian Hu, Gene H. McAllister. 85-88 [doi]
- A dual-band triple-mode SoC for 802.11a/b/g Embedded WLAN in 90nm CMOSAlireza Shirvani, Derek Cheung, Randy Tsang, Shafiq Jamal, Thomas Cho, Xiaodong Jin, Yonghua Song. 89-92 [doi]
- Design and implementation of a reconfigurable heterogeneous multiprocessor SoCMassimo Bocchi, Mario de Dominicis, Claudio Mucci, Antonio Deledda, Fabio Campi, Andrea Lodi 0002, Mario Toma, Roberto Guerrieri. 93-96 [doi]
- Embedded Mixed-Signal IP Development Methodology in 90nm CMOS SerDes FPGAsRakesh H. Patel, William Bereza. 97-100 [doi]
- Integrated 155M-10Gbps Framer with 22.5Gbps Low/High Order Cross Connect SoCK. Venkataraman, V. Suresh, S. Iyengar, M. Ott, S. R. Kalari, J. Zhi, E. Ruetz, M. Gray, B. Reynov, A. Iqbal. 101-104 [doi]
- Comparison and Impact of Substrate Noise Generated by Clocked and Clockless Digital CircuitryJim Le, Christopher Hanken, Martin Held, Michael S. Hagedorn, Kartikeya Mayaram, Terri S. Fiez. 105-108 [doi]
- A Multi-Nodes Human Body Communication Sensor Network Control ProcessorSungdae Choi, Seong-Jun Song, Kyomin Sohn, Hyejung Kim, Joo-Young Kim, Namjun Cho, Jeong-Ho Woo, Jerald Yoo, Hoi-Jun Yoo. 109-112 [doi]
- Challenges in Designing Low-Power CMOS Wireless Systems-on-a-ChipDavid Su. 113-120 [doi]
- A 2.4GHz direct modulated 0.18μm CMOS IEEE 802.15.4 compliant Transmitter for ZigBeeS. Beyer, R. Jaehne, W. Kluge, D. Eggert. 121-124 [doi]
- A Wideband ΔΣ Digital-RF Modulator With Self-Tuned RF Bandpass Reconstruction FilterAlbert Jerng, Charles G. Sodini. 125-128 [doi]
- Quad Band Digitally Controlled Oscillator for WCDMA Transmitter in 90nm CMOSSiray Akhtar, Mehmet Ipek, J. Lin, Robert Bogdan Staszewski, Petteri Litmanen. 129-132 [doi]
- Low-power CMOS IEEE 802.11a/g Signal Separator for Outphasing TransmitterLuigi Panseri, Luca Romanò, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita. 133-136 [doi]
- A Novel DAC Based Switching Power Amplifier for Polar TransmitterAmin Shameli, Aminghasem Safarian, Ahmadreza Rofougaran, Maryam Rofougaran, Franco De Flaviis. 137-140 [doi]
- A 1.2V, 2.4GHz Fully Integrated Linear CMOS Power Amplifier with Efficiency EnhancementGang Liu, Tsu-Jae King Liu, Ali M. Niknejad. 141-144 [doi]
- A 4mW per-Channel 101dB-DR Stereo Audio DAC with Transformed Quantization StructureYong-Hee Lee, Moo-Yeol Choi, Seung-Bin You, Wang-Seup Yeum, Ho-Jin Park, Jae-Whui Kim. 145-148 [doi]
- Design of a binary-weighted resistor DAC using tunable linearized floating-gate CMOS resistorsErhan Ozalevli, Huseyin Dinc, Haw-Jing Lo, Paul E. Hasler. 149-152 [doi]
- Low Power Approaches to High Speed CMOS Current Steering DACsDouglas A. Mercer. 153-160 [doi]
- An Area Optimized 2.5-V 10-b 200-MS/s 200-μA CMOS DACBabak Nejati, Lawrence Larson. 161-164 [doi]
- A 10-bit 1GSample/s DAC in 90nm CMOS for Embedded ApplicationsJing Cao, Haiqing Lin, Yihai Xiang, Chungpao Kao, Ken Dyer. 165-168 [doi]
- Implications of Proximity Effects for Analog DesignPatrick G. Drennan, M. L. Kniffin, D. R. Locascio. 169-176 [doi]
- Verification of Complex Analog Integrated CircuitsKenneth S. Kundert, Henry Chang. 177-184 [doi]
- On-the-Fly Fidelity Assessment for Trajectory-Based Circuit MacromodelsSaurabh K. Tiwary, Rob A. Rutenbar. 185-188 [doi]
- Predictive Modeling of the NBTI Effect for Reliable DesignSarvesh Bhardwaj, Wenping Wang, Rakesh Vattikonda, Yu Cao, Sarma B. K. Vrudhula. 189-192 [doi]
- Modeling, Design, and Verification for the Analog Front-end of a MEMS-based Parallel Scanning-probe Storage DeviceChristoph Hagleitner, Anthony R. Bonaccio, Hugo E. Rothuizen, Dorothea Wiesmann, Jan Lienemann, Jan G. Korvink, Giovanni Cherubini, Evangelos Eleftheriou. 193-196 [doi]
- Modeling Op Amp Nonlinearity in Switched-Capacitor Sigma-Delta ModulatorsKhaled Abdelfattah, Behzad Razavi. 197-200 [doi]
- Rapid Simulation of Current Steering Digital-to-Analog Converters using Verilog-AMurali Shanmugasundaram, Shanthi Pavan. 201-204 [doi]
- nd-Order ΔΣ Frequency DigitizerMohammad Sharifkhani, Manoj Sachdev. 205-208 [doi]
- A CMOS 15-Bit 125-MS/s Time-Interleaved ADC with Digital Background CalibrationZwei-Mei Lee, Cheng-Yeh Wang, Jieh-Tsorng Wu. 209-212 [doi]
- A Low 1/f Noise CMOS Low-Dropout Regulator with Current-Mode Feedback Buffer AmplifierWonseok Oh 0002, Bertan Bakkaloglu, Bhaskar Aravind, Siew Kuok Hoon. 213-216 [doi]
- 10-b 100-MS/s Two-Channel Time-Interleaved Pipelined ADCKamal El-Sankary, Mohamad Sawan. 217-220 [doi]
- A 20 GS/sec Analog-to-Digital Sigma-Delta Modulator in SiGe HBT TechnologyXiangtao Li, Wei-Min Lance Kuo, Yuan Lu, John D. Cressler. 221-224 [doi]
- A 300 °C, 110-dB Sigma-Delta Modulator with Programmable Gain in Bulk CMOSXinyu Yu, Steven L. Garverick. 225-228 [doi]
- A 0.18μm CMOS 1000 frames/sec, 138dB Dynamic Range Readout Circuit for 3D-IC IR Focal Plane ArraysSam Kavusi, Kunal Ghosh, Keith Fife, Abbas El Gamal. 229-232 [doi]
- ViPro: Focal-Plane Spatially-Oversampling CMOS Image Compression SensorAshkan Olyaei, Roman Genov. 233-236 [doi]
- Prediction and Characterization of Frequency Dependent MOS Switch Linearity and the Design ImplicationsThomas William Brown, Terri S. Fiez, Mikko Hakkarainen. 237-240 [doi]
- 1.56 GHz On-chip Resonant Clocking in 130nm CMOSMartin Hansson, Behzad Mesgarzadeh, Atila Alvandpour. 241-244 [doi]
- Low-Ripple CMOS Switched-Capacitor Power Converter With Closed-Loop Interleaving RegulationMohankumar N. Somasundaram, Dongsheng Ma. 245-248 [doi]
- A Low Power ASK Clock and Data Recovery Circuit for Wireless Implantable ElectronicsHong Yu, Rizwan Bashirullah. 249-252 [doi]
- An Efficient Adaptive Digital DC-DC Converter with Dual Loop Controls for Fast Dynamic Voltage ScalingJanghoon Song, Gilwon Yoon, Chulwoo Kim. 253-256 [doi]
- A Floating-gate Based Low-Power Capacitive Sensing Interface CircuitSheng-Yu Peng, Muhammad Shakeel Qureshi, Arindam Basu, Paul E. Hasler, Levent Degertekin. 257-260 [doi]
- Pulsenet - A Parallel Flash Sampler and Digital Processor IC for Optical SETIAndrew W. Howard, Gu-Yeon Wei, William J. Dally, Paul Horowitz. 261-264 [doi]
- A 32Gb/s On-chip Bus with Driver Pre-emphasis SignalingLiang Zhang, John Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, Paul D. Franzon. 265-268 [doi]
- An Integrated 90V Switch Array for Medical Ultrasound ApplicationsYe-Ming Li, Robert Wodnicki, Naveen Chandra, Naresh Rao. 269-272 [doi]
- Towards a Wearable Electronic Nose ChipKea-Tiong Tang, R. M. Goodman. 273-276 [doi]
- A 1V 420μW 32-channel Cortical Signal InterfaceEdward K. F. Lee, Eusebiu Matei, Anthony Lam, Taihu Li. 277-280 [doi]
- A 3D Multi-Aperture Image Sensor ArchitectureKeith Fife, Abbas El Gamal, H.-S. Philip Wong. 281-284 [doi]
- GHz Serial Passive Clock Distribution in VLSI Using Bidirectional SignalingVladimir I. Prodanov, Mihai Banu. 285-288 [doi]
- A Driving Scheme for AMOLED Displays Based on Current FeedbackShahin J. Ashtiani, Arokia Nathan. 289-292 [doi]
- Efficient Far-Field Radio Frequency Power Conversion System for Passively Powered Sensor NetworksTriet Le, Kartikeya Mayaram, Terri S. Fiez. 293-296 [doi]
- Match Line Sense Amplifiers with Positive Feedback for Low-Power Content Addressable MemoriesNitin Mohan, Wilson Fung, Derek Wright, Manoj Sachdev. 297-300 [doi]
- A Soft-Error Tolerant Content-Addressable Memory (CAM) Using An Error-Correcting-Match SchemeKostas Pagiamtzis, Navid Azizi, Farid N. Najm. 301-304 [doi]
- 180nm 4Mb High Speed High Reliability Embedded SONOS Flash MemoryLiyang Pan, Dong Wu, Guangjun Yang, Lei Sun, Huiqing Pang, Jun Zhu. 305-308 [doi]
- A Low-Power Routing Architecture Optimized for Deep Sub-Micron FPGAsLuca Ciccarelli, D. Loparco, Massimiliano Innocenti, A. Lodi, Claudio Mucci, Pier Luigi Rolandi. 309-312 [doi]
- A 0.13 μm Low-power Race-free Programmable Logic ArrayGiby Samson, Lawrence T. Clark. 313-316 [doi]
- An Energy Scalable Computational Array for Sensor Signal ProcessingLiping Guo, Mackenzie R. Scott, Rajeevan Amirtharajah. 317-320 [doi]
- Nonlinear Soft-Output Signal Detector Design and Implementation for MIMO Communication Systems with High Spectral EfficiencySizhong Chen, Fei Sun, Tong Zhang 0002. 321-324 [doi]
- VLSI Design of High-Rate Quasi-Cyclic LDPC Codes for Magnetic Recording ChannelHao Zhong, Tong Zhang 0002, Erich F. Haratsch. 325-328 [doi]
- A CMOS Image Sensor with combined adaptive-quantization and QTD-based on-chip compression processorShoushun Chen, Amine Bermak, Wang Yan, Dominique Martinez. 329-332 [doi]
- Considerations for Accurate Behavioral Modeling of High-Speed SC ΣΔ ModulatorsGeorge Suárez Martínez, Manuel Jiménez-Cedeño. 333-336 [doi]
- Width Quantization Aware FinFET Circuit DesignJie Gu, John Keane, Sachin S. Sapatnekar, Chris H. Kim. 337-340 [doi]
- Concurrent Design of Delta-Sigma Modulator Using Behavioral Modeling and Simulation with the Verilog-AT. Yamamoto, T. Suzuki, Hideki Asai. 341-344 [doi]
- IO Clock Network Skew & Performance Analysis: A Pentium-D Case StudyVishal Bhargava, N. Haider, N. Sarpotdar. 345-348 [doi]
- Nonlinear Phase Macromodel Based Simulation/Design of PLLs with Superharmonically Locked DividersShweta Srivastava, Xiaolue Lai, Jaijeet S. Roychowdhury. 349-352 [doi]
- The Backward-traversing Relaxation Algorithm for Circuit SimulationChun-Jung Chen, Tai-Ning Yang, Jenn-Dong Sun. 353-356 [doi]
- Yield and Cost Modeling for 3D Chip Stack TechnologiesP. Mercier, S. R. Singh, K. Iniewski, B. Moore, P. O'Shea. 357-360 [doi]
- On-Chip Transient Detection Circuit for System-Level ESD Protection in CMOS ICsMing-Dou Ker, Cheng-Cheng Yen, Pi-Chia Shih. 361-364 [doi]
- CMOS Mixed-Signal Circuit Process Variation Sensitivity Characterization for Yield ImprovementDaeik D. Kim, Choongyeun Cho, Jonghae Kim, Jean-Olivier Plouchart, Robert Trzcinski, David Ahlgren. 365-368 [doi]
- In Situ Evaluation Method for On-Chip Inductors Using Oscillator ResponseMizuki Motoyoshi, Minoru Fujishima. 369-372 [doi]
- A Quadrature Demodulator for WCDMA Receiver Using Common-Base Input Stage with Robustness to Transmitter LeakageToshiya Mitomo, Osamu Watanabe 0003, Ryuichi Fujimoto, Shunji Kawaguchi. 373-376 [doi]
- A 3.8-5.5-GHz Multi-Band CMOS Frequency Synthesizer for WPAN/WLAN ApplicationsJa-Yol Lee, Kwi-Dong Kim, Jong-Kee Kwon, Seung-Chul Lee, Jongdae Kim, Sang-Heung Lee. 377-380 [doi]
- Inductor- and Transformer-based Integrated RF Oscillators: A Comparative StudyHarish Krishnaswamy, Hossein Hashemi. 381-384 [doi]
- An 8-mW, ESD-protected, CMOS LNA for Ultra-Wideband ApplicationsKaran S. Bhatia, Sami Hyvonen, Elyse Rosenbaum. 385-388 [doi]
- X/Ku Band CMOS LNA Design TechniquesBagher Afshar, Ali M. Niknejad. 389-392 [doi]
- A 60GHz Phased Array in CMOSSayf Alalusi, Robert W. Brodersen. 393-396 [doi]
- A 44GHz Dual-Modulus Divide-by-4/5 Prescaler in 90nm CMOS TechnologyChihun Lee, Lan-chou Cho, Shen-Iuan Liu. 397-400 [doi]
- A Multi-Standard Low Power 1.5-3.125 Gb/s Serial Transceiver in 90nm CMOSD. A. Yokoyama-Martin, K. Krishna, J. Stonick, A. Caffee, E. K. Gamble, C. Jones, J. Mcneal, J. Parker, R. Segelken, J. Sonntag, K. Umino, J. Upton, D. Weinlader, S. Wolfer. 401-404 [doi]
- FEXT Crosstalk Cancellation for High-Speed Serial Link DesignKin-Joe Sham, Mahmoud Reza Ahmadi, S. B. Gerry Talbot, Ramesh Harjani. 405-408 [doi]
- A Low-Jitter Added SSCG with Seamless Phase Selection and Fast AFC for 3rd Generation Serial-ATAJongshin Shin, Ilwon Seo, Jiyoung Kim, Seung-Hee Yang, Chiwon Kim, Jaehyun Park, Hyungoo Kim, Myoungbo Kwak, GhyBoong Hong. 409-412 [doi]
- A 5Gb/s Transmitter with Reflection Cancellation for Backplane TransceiversRicky Yuen, Marcus van Ierssel, Ali Sheikholeslami, William W. Walker, Hirotaka Tamura. 413-416 [doi]
- Phase Mismatch Detection and Compensation for PLL/DLL Based Multi-Phase Clock GeneratorAmber Han-Yuan Tan, Gu-Yeon Wei. 417-420 [doi]
- Device Technology for embedded DRAM utilizing stacked MIM(Metal-Insulator-Metal) CapacitorYasushi Yamagata, Hiroki Shirai, Hirotoshi Sugimura, S. Arai, Tomoko Wake, Ken Inoue, Takashi Sakoh, Masato Sakao, Takaho Tanigawa. 421-427 [doi]
- A Scalable ET2RAM (SETRAM) with Verify Control for SoC Platform Memory IP on SOIKazutami Arimoto, Fukashi Morishita, Isamu Hayashi, Tetsushi Tanizaki, Takashi Ipposhi, Katsumi Dosaka. 429-432 [doi]
- Optimization of Surface Orientation for High-Performance, Low-Power and Robust FinFET SRAMSaakshi Gangwal, Saibal Mukhopadhyay, Kaushik Roy. 433-436 [doi]
- Spreading Diversity in Multi-cell Neutron-Induced Upsets with Device ScalingEishi Ibe, S. S. Chung, ShiJie Wen, Hironaru Yamaguchi, Yasuo Yahagi, Hideaki Kameyama, Shigehisa Yamamoto, Takashi Akioka. 437-444 [doi]
- Low Cost Test of High Bandwidth Embedded MemoriesKevin W. Gorman, Darren Anand, Gary Pomichter, William R. Corbin. 445-448 [doi]
- High-Temperature, High Reliability EEPROM Design For Automotive ApplicationsJ. Walsh, G. Scott. 449-452 [doi]
- Self-referenced sense amplifier for across-chip-variation immune sensing in high-performance Content-Addressable MemoriesIgor Arsovski, Reid Wistort. 453-456 [doi]
- Integrated MEMS Switches for Leakage Control of Battery Operated SystemsArijit Raychowdhury, Jeong I. Kim, Dimitrios Peroulis, Kaushik Roy. 457-460 [doi]
- CNT based mechanical devices for ULSI memoryJae Eun Jang, Seung Nam Cha, Youngjin Choi, Dae Joon Kang, Tim P. Butler, David G. Hasko, Jong-Min Kim, Gehan A. J. Amaratunga. 461-464 [doi]
- Nucleic Acid Extraction, Amplification, and Detection on Si-based Microfluidic PlatformsLevent Yobas, Hongmiao Ji, Wing-Cheong Hui, Yu Chen, Tit Meng Lim, Chew-Kiat Heng, Dim-Lee Kwong. 465-472 [doi]
- Silicon Integrated Circuits Incorporating AntennasK. O. Kenneth, Kihong Kim, Brian A. Floyd, Jesal L. Mehta, Hyun Yoon, Chih-Ming Hung, Daniel F. Bravo, Timothy O. Dickson, Xiaoling Guo, Ran Li, Narasimhan Trichy, James Caserta, Wayne R. Bomstad II, Jason Branch, Dong-Jun Yang, Jose L. Bohorquez, Jie Chen, E.-Y. Seok, Joe E. Brewer, Li Gao, Aravind Sugavanam, Jau-Jr Lin, Y. Su, Changhua Cao, M.-H. Hwang, Y.-P. Ding, Z. Li, S.-H. Hwang, H. Wu, Swaminathan Sankaran, N. Zhang. 473-480 [doi]
- Frequency-Based Measurement of Mismatches Between Small CapacitorsAshutosh Verma, Behzad Razavi. 481-484 [doi]
- A Calibration-Free 14b 70MS/s 3.3mm2 235mW 0.13um CMOS Pipeline ADC with High-Matching 3-D Symmetric CapacitorsYoung-Jae Cho, Kyung-Hoon Lee, Hee-Cheol Choi, Seung-Hoon Lee, Kyoung-Ho Moon, Jae-Whui Kim. 485-488 [doi]
- A 3.5 GS/s 5-b Flash ADC in 90 nm CMOSSunghyun Park, Yorgos Palaskas, Ashoke Ravi, Ralph E. Bishop, Michael P. Flynn. 489-492 [doi]
- A 30-GS/sec Track and Hold Amplifier in 0.13-μm CMOS TechnologyShahriar Shahramian, Sorin P. Voinigescu, Anthony Chan Carusone. 493-496 [doi]
- A 10b 25MS/s 4.8mW 0.13um CMOS ADC for Digital Multimedia Broadcasting ApplicationsYoung-Jae Cho, Doo-Hwan Sa, Yong Woo Kim, Kyung-Hoon Lee, Hee-Cheol Choi, Seung-Hoon Lee, Young-Deuk Jeon, Seung-Chul Lee, Jong-Kee Kwon. 497-500 [doi]
- A 1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D ConvertersTakeshi Ueno, Tomohiko Ito, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura. 501-504 [doi]
- Low-Power Design of Pipeline A/D ConvertersShoji Kawahito. 505-512 [doi]
- A 1.8-V 22-mW 10-bit 30-MS/s Subsampling Pipelined CMOS ADCJian Li, Xiaoyang Zeng, Lei Xie, Jun Chen, Jianyun Zhang, Yawei Guo. 513-516 [doi]
- Digital Signal Processing for RF at 45-nm CMOS and BeyondRobert Bogdan Staszewski, Khurram Muhammad, Dirk Leipold. 517-522 [doi]
- Delta-Sigma Modulation in Direct Digital Frequency SynthesisDayu Yang, Weining Ni, Fa Foster Dai, Yin Shi, Richard C. Jaeger. 523-526 [doi]
- OFDM modulator with digital IF and on-chip D/A-converterJonne Lindeberg, Olli Väänänen, Jussi Pirkkalaniemi, Marko Kosunen, Kari Halonen. 527-530 [doi]
- Neuromorphic Vision Systems for Mobile ApplicationsRalph Etienne-Cummings, Swati Mehta, Ralf M. Philipp, Viktor Gruev. 531-534 [doi]
- A Low-Power Unified Arithmetic Unit for Programmable Handheld 3-D Graphics SystemsByeong-Gyu Nam, Hyejung Kim, Hoi-Jun Yoo. 535-538 [doi]
- A Scalable 7.2 Mb/s 3GPP HSDPA Co-processor with Advanced NLMS Receiver and Receive Diversity for Mobile TerminalsC. Thomas, M. Cooke, O. Ridler, K. van den Beld, D. Yip, U. Sontowski, Adriel Kind, Gongyu Zhou, Yi-Chen Li, Long Ung, R. Banna, Benjamin Widdup, Tom Prokop, Mark Bickerstaff, Graeme Woodward, R. Srikantiah, K. Gupta, R. Reddy, S. Arvapalli, R. Bidnur, A. V. S. S. Prasad, R. Lang, Chris Nicol. 539-542 [doi]
- A GFLOPS Vector-DSP for Broadband Wireless ApplicationsE. Matu, Hendrik Seidel, Torsten Limberg, Pablo Robelly, Gerhard Fettweis. 543-546 [doi]
- SRAMs in Scaled Technologies under Process Variations: Failure Mechanisms, Test & Variation Tolerant DesignSaibal Mukhopadhyay, Amit Agarwal, Qikai Chen, Kaushik Roy. 547-554 [doi]
- The UltraSPARC T1 Processor: CMT ReliabilityAna Sonia Leon, Brian Langley, Jinuk Luke Shin. 555-562 [doi]
- A Time-Slicing Ring Oscillator for Capturing Instantaneous Delay Degradation and Power Supply Voltage DropTakashi Sato, Yu Matsumoto, Koji Hirakimoto, Michio Komoda, Junichi Mano. 563-566 [doi]
- Design For At-Speed Structural Test And Performance Verification Of High-Performance ASICsVikram Iyengar, Mark Johnson, Theo Anemikos, Gary Grise, Mark Taylor, Raymond Farmer, Frank Woytowich, Bob Bassett. 567-570 [doi]
- Robust Inductor Design for RF CircuitsYin-Lung Ryan Lu, Yung-Huei Lee, William J. Mcmahon, Tze-Ching Fung. 571-574 [doi]
- Chip-to-Chip Inductive Wireless Power Transmission System for SiP ApplicationsKohei Onizuka, Hiroshi Kawaguchi, Makoto Takamiya, Tadahiro Kuroda, Takayasu Sakurai. 575-578 [doi]
- Balanced Low Noise High Dynamic Photodiode Interface for AutomotiveI. Koudar. 579-582 [doi]
- On-chip Digitally Tunable High Voltage Generator for Electrostatic Control of Micromechanical DevicesLasse Aaltonen, Mikko Saukoski, Kari Halonen. 583-586 [doi]
- Die Stacking Technology for Terabit Chip-to-Chip CommunicationsArifur Rahman, John Trezza, Bernard J. New, Stephen Trimberger. 587-590 [doi]
- Wireline Equalization using Pulse-Width ModulationJan H. Rutger Schrader, Eric A. M. Klumperink, Jan L. Visschers, Bram Nauta. 591-598 [doi]
- A 10Gbps Burst-Mode CDR Circuit in 0.18μm CMOSChe-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu. 599-602 [doi]
- A 1.6Gbps Digital Clock and Data Recovery CircuitPavan Kumar Hanumolu, Min Gyu Kim, Gu-Yeon Wei, Un-Ku Moon. 603-606 [doi]
- A Sub-i V Low-Noise Bandgap Voltage ReferenceKeith E. Sanborn, Dongsheng Ma, Vadim V. Ivanov. 607-610 [doi]
- A Compact Programmable CMOS Reference With ±40μV AccuracyVenkatesh Srinivasan, Guillermo J. Serrano, Christopher M. Twigg, Paul E. Hasler. 611-614 [doi]
- A Transient-Enhanced 20μA-Quiescent 200mA-Load Low-Dropout Regulator With Buffer Impedance AttenuationMohammad A. Al-Shyoukh, Raul A. Perez, Hoi Lee. 615-618 [doi]
- Compact outside-rail circuit structure by single-cascode two-transistor topologyAtit Tamtrakarn, Hiroki Ishikuro, Koichi Ishida, Takayasu Sakurai. 619-622 [doi]
- Enhancing Productivity by Continuously Improving Standard Compact ModelsJ. Watts. 623-630 [doi]
- A Web Tool for Interactive Exploration of Analog Design TradeoffsCynthia L. Recker, Brandt Braswell, Patrick G. Drennan, Colin C. McAndrew. 631-634 [doi]
- Circuit Optimization Using Scale Based SensitivitiesBhavna Agrawal, Frank Liu, Sani R. Nassif. 635-638 [doi]
- A 4-Channel High-Precision Constant Current Control ASIC for Automotive Transmission ApplicationsW. Horn, M. Grafling, G. Gross, M. Steiner, J. Treiber, R. Dickman, K. Reis. 639-642 [doi]
- Ditherng Skip Modulator with a Width Controller for Ultra-wide-load High-Efficiency DC-DC ConvertersHong-Wei Huang, Hsin-Hsin Ho, Chieh-Ching Chien, Ke-Horng Chen, Gin-Kou Ma, Sy-Yen Kuo. 643-646 [doi]
- Per-Pixel Floating-Point ADCs with Electronic Shutters for a High Dynamic Range, High Frame Rate Infrared Focal Plane ArraySang Min Lee, Hyunsik Park, Bruce A. Wooley. 647-650 [doi]
- Smart CMOS Charge Transfer Readout Circuit for Time Delay and Integration ArraysChul Bum Kim, Byung Hyuk Kim, Yong Soo Lee, Han Jung, Hee Chul Lee. 651-654 [doi]
- A 104dB SNDR Transimpedance-based CMOS ASIC for Tuning Fork MicrogyroscopesAjit Sharma, Faisal Zaman, Farrokh Ayazi. 655-658 [doi]
- Fully-Integrated CMOS Power Regulator for Telemetry-Powered Implantable Biomedical MicrosystemsAmir M. Sodagar, Khalil Najafi, Kensall D. Wise, Maysam Ghovanloo. 659-662 [doi]
- Notice of Violation of IEEE Publication PrinciplesA Varactor-Less 10GHz CMOS LC-VCO for Optical Communications Transceiver SOCs Using Caged InductorsA. Maxim. 663-670 [doi]
- An Ultra Compact Differentially Tuned 6 GHz CMOS LC VCO with Dynamic Common-Mode FeedbackBaharak Soltanian, Herschel A. Ainspan, Woogeun Rhee, Daniel J. Friedman, Peter R. Kinget. 671-674 [doi]
- Mutual Injection Pulling Between OscillatorsBehzad Razavi. 675-678 [doi]
- Technologies for (sub-) 45nm Analog/RF CMOS - Circuit Design Opportunities and ChallengesStefaan Decoutere, Piet Wambacq, Vaidy Subramanian, Jonathan Borremans, Abdelkarim Mercha. 679-686 [doi]
- Recent Advances in III-V ElectronicsYing-Kuang Chen, Yves Baeyens, Nils Weimann, Jaesik Lee, Joe Weiner, Vincent Houtsma, Y. Yang. 687-690 [doi]
- Electrical Characteristic Fluctuations in Sub-45nm CMOS DevicesFu-Liang Yang, Jiunn-Ren Hwang, Yiming Li. 691-694 [doi]
- SiGe BiCMOS Trends - Today and TomorrowJames S. Dunn, David L. Harame, Alvin J. Joseph, Stephen A. St. Onge, Natalie B. Feilchenfeld, Louis D. Lanzerotti, Bradley A. Orner, E. G. Gebreselasie, Jeffrey B. Johnson, Douglas D. Coolbaugh, R. Rassel, M. Khater. 695-702 [doi]
- Advances and Challenges in Flip-Chip PackagingR. Mahajan, D. Mallik, R. Sankman, K. Radhakrishnan, C. Chiu, J. He. 703-709 [doi]
- Compact modeling of noise in CMOSAndries J. Scholten, Ronald van Langevelde, Luuk F. Tiemeijer, Dick B. M. Klaassen. 711-716 [doi]
- A Scalable Model Methodology for Octagonal Differential and Single-Ended InductorsVolker Blaschke, James Victory. 717-720 [doi]
- Measurement of Inductive Coupling Effect on Timing in 90nm Global InterconnectsYasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye. 721-724 [doi]
- A Novel Monitoring Method of RF Characteristics Variations for Sub-0.1μm MOSFETs with Precise Gate-resistance ModelAkira Tanabe, Ken'ichiro Hijioka, Yoshihiro Hayashi. 725-728 [doi]
- Sizing Ground Taps to Minimize Substrate Noise Coupling in RF LNAsArathi Sundaresan, Terri S. Fiez, Kartikeya Mayaram. 729-732 [doi]
- First-Harmonic Injection-Locked Ring OscillatorsBehzad Mesgarzadeh, Atila Alvandpour. 733-736 [doi]
- Analysis of Oscillators Locked by Large Injection Signals: Generalized Adler's Equation and Geometrical InterpretationAhmad Mirzaei, Mohammad E. Heidari, Asad A. Abidi. 737-740 [doi]
- Rigorous Analytical/Graphical Injection Locking Analysis of Two-Port Negative Resistance OscillatorsTing Mei, Jaijeet S. Roychowdhury. 741-744 [doi]
- A Digital PLL with 5-Phase Digital PFD for Low Long-term Jitter Clock RecoveryTae-young Oh, Seung-Hyun Yi, Sung-Hyun Yang, Byong Chan Lim, Kuk-Tae Hong. 745-748 [doi]
- Adaptive-Bandwidth Mixing PLL/DLL Based Multi-Phase Clock Generator for Optimal Jitter PerformanceAmber Han-Yuan Tan, Gu-Yeon Wei. 749-752 [doi]
- A Low Jitter Multi-Phase PLL with Capacitive CouplingJunyoung Park, Michael P. Flynn. 753-756 [doi]
- A 150MHz-400MHz DLL-Based Programmable Clock Multiplier with -7OdBc Reference Spur in 0.18um CMOSPrabir C. Maulik, Douglas A. Mercer. 757-760 [doi]
- An Anti-Harmonic Locking, DLL Frequency Multiplier with Low Phase Noise and Reduced SpurQingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski. 761-764 [doi]
- Integrated VCO Design for MICS TransceiversAhmet Tekin, Mehmet R. Yuce, Wentai Liu. 765-768 [doi]
- A 0.8V 1.52MHz MSVC Relaxation Oscillator with Inverted Mirror Feedback Reference for UHF RFIDRaymond E. Barnett, Jin Liu. 769-772 [doi]
- A 36Gb/s ACCI Multi-Channel Bus using a Fully Differential Pulse ReceiverLei Luo, John M. Wilson, Stephen Mick, Jian Xu, Liang Zhang, Evan Erickson, Paul D. Franzon. 773-776 [doi]
- 900MHz to 1.2GHz Two-Phase Resonant Clock Network with Programmable Driver and LoadingJuang-Ying Chueh, Visvesh S. Sathe, Marios C. Papaefthymiou. 777-780 [doi]
- Clock Generation and Distribution Using Traveling-Wave Oscillators with Reflection and RegenerationRuilin Wang, Cheng-Kok Koh, Byunghoo Jung, William J. Chappell. 781-784 [doi]
- Injection-Locked Clocking: A New GHz Clock Distribution SchemeLin Zhang, Berkehan Ciftcioglu, Michael C. Huang, Hui Wu. 785-788 [doi]
- Digital RF Processor Techniques for Single-Chip RadiosRobert Bogdan Staszewski, Khurram Muhammad, Dirk Leipold. 789-796 [doi]
- A 1.5V 0.7-2.5GHz CMOS Quadrature Demodulator for Multi-Band Direct-Conversion ReceiversNuntachai Poobuapheun, Wei-Hung Chen, Zdravko Boos, Ali M. Niknejad. 797-800 [doi]
- A 1.5-V CMOS Receiver Front-End for 9-Band MB-OFDM UWB SystemShuzuo Lou, Hui Zheng, Howard C. Luong. 801-804 [doi]
- A Distributed RF Front-End for UWB ReceiversAminghasem Safarian, Lei Zhou, Payam Heydari. 805-808 [doi]
- A Fully-Integrated 0.11μm CMOS Digital Low-IF DVB-S2 Satellite TV Dual Tuner SOCA. Maxim, R. K. Poorfard, R. Johnson, P. Crawley, J. Kao, Z. Dong, M. Chennam, T. Nutt, D. S. Trager. 809-812 [doi]
- Active On-Die Suppression of Power Supply NoiseGökçe Keskin, Xin Li, Lawrence T. Pileggi. 813-816 [doi]
- A Fully Integrated DC/DC Converter for Tunable RF FiltersMohamed Bouhamame, Jean-Robert Tourret, Luca Lo Coco, Serge Toutain, Olivier Pasquier. 817-820 [doi]
- A Time Domain Mixed-Mode Temperature Sensor with Digital Set-Point ProgrammingPoki Chen, Chun-Chi Chen, Tuo-Kuang Chen, Shi-Wei Chen. 821-824 [doi]
- A Unity-Gain Buffer with Reduced Offset and Gain ErrorGuangmao Xing, Stephen H. Lewis, T. R. Viswanathan. 825-828 [doi]
- m-Boosted Cascode in 0.18-μm CMOSMasum Hossain, Anthony Chan Carusone. 829-832 [doi]
- A 0.6V Highly Linear Switched-R-MOSFET-C FilterPeter Kurahashi, Pavan Kumar Hanumolu, Gabor C. Temes, Un-Ku Moon. 833-836 [doi]
- Fast Automatic Tuning of Channel Selection Filters Based on Phase Delay CalibrationKoutani Kagoshima, Shuichi Kawama, Shinji Toyoyama, Kunihiko Iizuka. 837-840 [doi]
- A Low Phase Noise 100MHz Silicon BAW Reference OscillatorKrishnakumar Sundaresan, Gavin K. Ho, Siavash Pourkamali, Farrokh Ayazi. 841-844 [doi]
- EDA Challenges in Nano-scale TechnologyJamil Kawa, Charles Chiang, Raul Camposano. 845-851 [doi]
- Statistical and Corner Modeling of Interconnect Resistance and CapacitanceNing Lu. 853-856 [doi]
- Experimental Verification of Simulation Based Yield Optimization for Power-On Reset CellsGerhard Rappitsch, Oliver Eisenberger, Bernd Obermeier, Andreas Ripp, Michael Pronath. 857-860 [doi]
- Measurement results of delay degradation due to power supply noise well correlated with full-chip simulationYasuhiro Ogasahara, Takashi Enami, Masanori Hashimoto, Takashi Sato, Takao Onoye. 861-864 [doi]
- Delay Variation Analysis in Consideration of Dynamic Power Supply Noise WaveformMitsuya Fukazawa, Makoto Nagata. 865-868 [doi]
- Crosstalk Reduction with Nonlinear Transmission Lines for High-Speed VLSI SystemJinsook Kim, Weiping Ni, Edwin C. Kan. 869-872 [doi]