P. Mercier, S. R. Singh, K. Iniewski, B. Moore, P. O'Shea. Yield and Cost Modeling for 3D Chip Stack Technologies. In Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006, DoubleTree Hotel, San Jose, California, USA, September 10-13, 2006. pages 357-360, IEEE, 2006. [doi]
Abstract is missing.