Rakesh H. Patel, William Bereza. Embedded Mixed-Signal IP Development Methodology in 90nm CMOS SerDes FPGAs. In Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006, DoubleTree Hotel, San Jose, California, USA, September 10-13, 2006. pages 97-100, IEEE, 2006. [doi]
Abstract is missing.