Derek Wright - researchr alias

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Viewing Publication 1 - 10 from 10

2025

FPGA Implementation of SNN Based Multiple Input Multiple Output Neurons Using LIF ModelYugal Kishore Maheshwari, Derek Wright, Manoj Sachdev. ccece 2025: 794-795 [doi]

2021

Ultra Low-power, Low-energy Static Single-phase Clocked Flip-flopYugal Maheshwari, Kleber Stangherlin, Derek Wright, Manoj Sachdev. icecsys 2021: 1-4 [doi]

Body Biased Sense Amplifier With Auto-Offset Mitigation for Low-Voltage SRAMsDhruv Patel, Adam Neale, Derek Wright, Manoj Sachdev. tcasI, 68(8):3265-3278, 2021. [doi]

2019

Hybrid Latch-Type Offset Tolerant Sense Amplifier for Low-Voltage SRAMsDhruv Patel, Adam Neale, Derek Wright, Manoj Sachdev. tcas, 66-I(7):2519-2532, 2019. [doi]

2018

Sense amplifier offset characterisation and test implications for low-voltage SRAMs in 65 nmDhruv Patel, Derek Wright, Manoj Sachdev. ets 2018: 1-6 [doi]

2009

A Low-Power Ternary CAM With Positive-Feedback Match-Line Sense AmplifiersNitin Mohan, Wilson Fung, Derek Wright, Manoj Sachdev. tcas, 56-I(3):566-573, 2009. [doi]

2006

Design techniques and test methodology for low-power TCAMsNitin Mohan, W. Fung, Derek Wright, Manoj Sachdev. tvlsi, 14(6):573-586, 2006. [doi]

Match Line Sense Amplifiers with Positive Feedback for Low-Power Content Addressable MemoriesNitin Mohan, Wilson Fung, Derek Wright, Manoj Sachdev. cicc 2006: 297-300 [doi]

2005

Co-Scheduling of Computation and Data on Computer ClustersAlexandru Romosan, Doron Rotem, Arie Shoshani, Derek Wright. ssdbm 2005: 103-112

2003

Transistor-Level Fault Analysis and Test Algorithm Development for Ternary Dynamic Content Addressable MemorieDerek Wright, Manoj Sachdev. itc 2003: 39-47 [doi]

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