A 8×5 Gb/s source-synchronous receiver with clock generator phase error correction

Ankur Agrawal, Pavan Kumar Hanumolu, Gu-Yeon Wei. A 8×5 Gb/s source-synchronous receiver with clock generator phase error correction. In Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, CICC 2008, DoubleTree Hotel, San Jose, California, USA, September 21-24, 2008. pages 459-462, IEEE, 2008. [doi]

Abstract

Abstract is missing.