Katsuro Sasaki - researchr alias

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Viewing Publication 1 - 7 from 7

1997

Instruction buffering to reduce power in processors for signal processingRaminder Singh Bajwa, Mitsuru Hiraki, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Koichi Seki, Katsuro Sasaki. tvlsi, 5(4):417-424, 1997. [doi]

1996

Stage-skip pipeline: a low power processor architecture using a decoded instruction bufferMitsuru Hiraki, Raminder Singh Bajwa, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Katsuro Sasaki, Koichi Seki. islped 1996: 353-358 [doi]

1995

Trends in low-power RAM circuit technologiesKiyoo Itoh, Katsuro Sasaki, Yoshinobu Nakagome. pieee, 83(4):524-543, 1995. [doi]

Half-swing clocking scheme for 75% power saving in clocking circuitryHirotsugu Kojima, Satoshi Tanaka, Katsuro Sasaki. jssc, 30(4):432-435, April 1995. [doi]

A 4.4 ns CMOS 54/spl times/54-b multiplier using pass-transistor multiplexerNorio Ohkubo, Makoto Suzuki, Toshinobu Shinbo, Toshiaki Yamanaka, Akihiro Shimizu, Katsuro Sasaki, Yoshinobu Nakagome. jssc, 30(3):251-257, March 1995. [doi]

A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuitsSuguru Tachibana, Hisayuki Higuchi, Koichi Takasugi, Katsuro Sasaki, Toshiaki Yamanaka, Yoshinobu Nakagome. jssc, 30(4):487-490, April 1995. [doi]

1994

A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiersKoichiro Ishibashi, Kunihiro Komiyaji, Sadayuki Morita, Toshiro Aoto, Shuji Ikeda, Kyoichiro Asayama, Atsuyosi Koike, Toshiaki Yamanaka, Naotaka Hashimoto, Haruhito Iida, Fumio Kojima, Koichi Motohashi, Katsuro Sasaki. jssc, 29(4):411-418, April 1994. [doi]

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