Mitsuru Hiraki - researchr alias

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Viewing Publication 1 - 13 from 13

2023

An On-Chip DC-DC Converter and Power Management System Achieving Zero Standby-to-Active Transition Time in MCUToyohiro Shimogawa, Makoto Nonaka, Toma Ogata, Toshiki Kiryu, Yasuto Igarashi, Kosuke Yayama, Masahiro Kitamura, Hiromichi Ishikura, Mitsuru Hiraki, Masao Ito, Takashi Kono. asscc 2023: 1-3 [doi]

2021

A CMOS Image Sensor and an AI Accelerator for Realizing Edge-Computing-Based Surveillance Camera SystemsFukashi Morishita, Norihito Kato, Satoshi Okubo, Takao Toi, Mitsuru Hiraki, Sugako Otani, Hideaki Abe, Yuji Shinohara, Hiroyuki Kondo. vlsic 2021: 1-2 [doi]

2020

A High-Precision Analog Front End Integrated in a 32bit Microcontroller for Industrial Sensing ApplicationsKoji Yoichi, Sugako Otani, Kazutoshi Tsuda, Naoya Tokimoto, Hideki Kamegawa, Yoshihisa Satou, Shioto Tanaka, Hideki Otsu, Mitsuru Hiraki, Masao Ito, Mitsuya Fukazawa, Hiroyuki Kondo. asscc 2020: 1-4 [doi]

2018

A Capacitance-to-Digital Converter Integrated in a 32bit Microcontroller for 3D Gesture SensingMitsuru Hiraki, Sugako Otani, Masao Ito, Takuya Mizokami, Masahiro Araki, Hiroyuki Kondo. asscc 2018: 269-272 [doi]

2004

A low-power microcontroller having a 0.5-/spl mu/A standby current on-chip regulator with dual-reference schemeMitsuru Hiraki, K. Fukui, Takayasu Ito. jssc, 39(4):661-666, 2004. [doi]

2002

A 63-/spl mu/W standby power microcontroller with on-chip hybrid regulator schemeMitsuru Hiraki, Takayasu Ito, Atsushi Fujiwara, Taichi Ohashi, Tetsuro Hamano, Takaaki Noda. jssc, 37(5):605-611, 2002. [doi]

1999

Pre-silicon parameter generation methodology using BSIM3 for device/circuit concurrent designMikako Miyama, Shiro Kamohara, Mitsuru Hiraki, Kazunori Onozawa, Hisaaki Kunitomo. cicc 1999: 359-363 [doi]

1997

Instruction buffering to reduce power in processors for signal processingRaminder Singh Bajwa, Mitsuru Hiraki, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Koichi Seki, Katsuro Sasaki. tvlsi, 5(4):417-424, 1997. [doi]

1996

Stage-skip pipeline: a low power processor architecture using a decoded instruction bufferMitsuru Hiraki, Raminder Singh Bajwa, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Katsuro Sasaki, Koichi Seki. islped 1996: 353-358 [doi]

1995

Data-dependent logic swing internal bus architecture for ultralow-power LSI'sMitsuru Hiraki, Hirotsugu Kojima, Hitoshi Misawa, Takashi Akazawa, Yuji Hatano. jssc, 30(4):397-402, April 1995. [doi]

1992

A 1.5-V full-swing BiCMOS logic circuitMitsuru Hiraki, Kazuo Yano, Masataka Minami, Kazushige Sato, Nozomu Matsuzaki, Atsuo Watanabe, Takashi Nishida, Katsuro Sasaki, Koichi Seki. jssc, 27(11):1568-1574, November 1992. [doi]

3.3-V BiCMOS circuit techniques for 250-MHz RISC arithmetic modulesKazuo Yano, Mitsuru Hiraki, Shoji Shukuri, M. Hanawa, Masato Suzuki, S. Morita, A. Kawamata, Nagatoshi Ohki, Takashi Nishida, Koichi Seki. jssc, 27(3):373-381, March 1992. [doi]

1991

Quasi-complementary BiCMOS for sub-3-V digital circuitsKazuo Yano, Mitsuru Hiraki, Shoji Shukuri, Yasuo Onose, Mitsuru Hirao, Nagatoshi Ohki, Takashi Nishida, Koichi Seki, Katsuhiro Shimohigashi. jssc, 26(11):1708-1719, November 1991. [doi]

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