Table of Contents

• Input-Adaptive and Regulated Multi-Output Power Management Unit for Wireless Power Reception and Distribution in Multi-Unit Implantable DevicesUnbong Lee, Doojin Jang, Wanyeong Jung, Minkyu Je. 1-4 [doi]
• 287-GHz CMOS Transceiver Pixel Array in a QFN Package for Active ImagingPranith R. Byreddy, Yukun Zhu, Harshpreet S. Bakshi, Kenneth K. O, Wooyeol Choi 0001. 1-4 [doi]
• AµProcessor Layer for mm-Scale Die-Stacked Sensing Platforms Featuring Ultra-Low Power Sleep Mode at 125°CJeongsup Lee, Yejoong Kim, Minchang Cho, Makoto Yasuda, Satoru Miyoshi, Masaru Kawaminami, David T. Blaauw, Dennis Sylvester. 1-4 [doi]
• A 2-Electrode ECG Amplifier with 0.5% Nominal Gain Shift and 0.13% THD in a 530mVpp Input Common-Mode RangeJiawei Xu, Zhiliang Hong. 1-4 [doi]
• Improved Design and In Vivo Animal Tests of Bone-Guided Cochlear Implant Microsystem with Monopolar Biphasic Multiple Stimulation and Neural Action Potential AcquisitionSung-Hao Wang, Yu-Kai Huang, Ching-Yuan Chen, Chia-Fone Lee, Chia-Hsiang Yang, Chung-Chih Hung, Chien-Hao Liu, Ming-Dou Ker, Chung-Yu Wu. 1-4 [doi]
• An Energy-efficient Multi-core Restricted Boltzmann Machine Processor with On-chip Bio-plausible Learning and Reconfigurable SparsityJiajun Wu, Xuan Huang, Le Yang, Liang Wang, Jipeng Wang, Zuozhu Liu, Kwen-Siong Chong, Shaowei Lin, Chao Wang. 1-4 [doi]
• A Power Efficient ECG Front-End with Input-Adaptive Gain Reaching 67.6-dB Dynamic RangeLiheng Liu, Yanlong Zhang, Li Dong 0007, Youze Xin, Shengwei Gao, Li Geng. 1-4 [doi]
• Supercomputer Fugaku: Co-designed with application developers/researchersToshiyuki Shimizu. 1-4 [doi]
• CompAcc: Efficient Hardware Realization for Processing Compressed Neural Networks Using Accumulator ArraysZexi Ji, Wanyeong Jung, Jongchan Woo, Khushal Sethi, Shih-Lien Lu, Anantha P. Chandrakasan. 1-4 [doi]
• A 0.4-1.7GHz Wide Range Fractional-N PLL Using a Transition-Detection DAC for Jitter ReductionJaekwang Yun, Sangyoon Lee, Yong-Un Jeong, Shin-Hyun Jeong, Suhwan Kim. 1-4 [doi]
• A Jitter-Tolerant Referenceless Digital-CDR for Cellular TransceiversJaekwon Kim, Youngjun Ko, Jahoon Jin, Jaehyuk Choi, Jung-Hoon Chun. 1-4 [doi]
• An 8.3% Efficiency 96-134 GHz CMOS Frequency Doubler Using Distributed Amplifier and Nonlinear Transmission LineShilei Hao, Yiwu Tang, Xuan Ding, Li Du, Yuan Du, Adrian Tang 0002, Qun Jane Gu, Mau-Chung Frank Chang. 1-2 [doi]
• A 186µW Glucose Monitoring SoC using Near-Infrared PhotoplethysmographyAminah Hina, Wala Saadeh. 1-4 [doi]
• Always-On, Sub-300-nW, Event-Driven Spiking Neural Network based on Spike-Driven Clock-Generation and Clock- and Power-Gating for an Ultra-Low-Power Intelligent DeviceDewei Wang, Pavan Kumar Chundi, Sung Justin Kim, Minhao Yang, Joao Pedro Cerqueira, Joonsung Kang, Seungchul Jung, Sang Joon Kim, Mingoo Seok. 1-4 [doi]
• An 8-mW 66-GHz Active Circulator with 40dB TX-RX Isolation in 65nm CMOS for Full-Duplex RadiosChendi Yu, Howard C. Luong. 1-4 [doi]
• A 10-b 900-MS/s Single-Channel Pipelined-SAR ADC Using Current-Mode Reference ScalingKang-Il Cho, Ho-Jin Kim, Jun-Ho Boo, Yong-Sik Kwak, Jun-Sang Park, Seung-Hoon Lee, Gil-Cho Ahn. 1-2 [doi]
• Co-optimization targeting future interconnectionWei Tsao, Da Sun, Chunlei Fan, Kuohsin Chen, Yingte Wang. 1-4 [doi]
• A 6.78-MHz Single-Stage Regulating Rectifier with Hysteretic Control and Current-Wave ModulationJie Lin, Chenchang Zhan, Yan Lu. 1-2 [doi]
• A 950-pW, 39-pJ/Conversion Leakage-Based Temperature-to-Digital Converter With 43mk ResolutionCheng-Ze Shao, Yu-Te Liao. 1-4 [doi]
• Intelligent Chips and Technologies for AIoT EraYu-Chin Hsu, Robert Chen-Hao Chang. 1-4 [doi]
• A 2.2mW 12-bit 200MS/s 28nm CMOS Pipelined SAR ADC with Dynamic Register-Based High-Speed SAR LogicJun-Sang Park, Je-Min Jeon, Jun-Ho Boo, Jae-Hyuk Lee, Kang-Il Cho, Ho-Jin Kim, Gil-Cho Ahn, Seung-Hoon Lee. 1-2 [doi]
• A Power-Efficient 13-Tap FIR filter and an IIR Filter Embedded in a 10-bit SAR ADCXin Xin, Linxiao Shen, Xiyuan Tang, Yi Shen 0007, Jueping Cai, Nan Sun. 1-4 [doi]
• A High-Precision Analog Front End Integrated in a 32bit Microcontroller for Industrial Sensing ApplicationsKoji Yoichi, Sugako Otani, Kazutoshi Tsuda, Naoya Tokimoto, Hideki Kamegawa, Yoshihisa Satou, Shioto Tanaka, Hideki Otsu, Mitsuru Hiraki, Masao Ito, Mitsuya Fukazawa, Hiroyuki Kondo. 1-4 [doi]
• A 17.7-pJ/Cycle ECG Processor for Arrhythmia Detection with High Immunity to Power Line Interference and Baseline DriftYue Yin, Syed Muhammad Abubakar, Songyao Tan, Hanjun Jiang, Zhihua Wang, Seng-Pan U, Wen Jia. 1-4 [doi]
• nd-Order CT ΔΣ ADC for Electrochemistry AcquisitionHao-Yun Lee, Peng-Wei Huang, Ding-Siang Ciou, Zhan-Xian Liao, Shuenn-Yuh Lee. 1-2 [doi]
• 2 in 40nmJinq Horng Teo, K. Ali, Massimo Alioto. 1-3 [doi]
• A 112-765 GOPS/W FPGA-based CNN Accelerator using Importance Map Guided Adaptive Activation Sparsification for Pix2pix ApplicationsWenyu Sun, Chen Tang, Zhuqing Yuan, Zhe Yuan, Huazhong Yang, Yongpan Liu. 1-4 [doi]
• A 50 Gb/s PAM-4 Transmitter with Feedforward Equalizer and Background Phase Error CalibrationYu-Ting Lin, Wei-Zen Chen. 1-2 [doi]
• A Dual-Mode Ground-Referenced Signaling Transceiver with a 3-Tap Feed-Forward Equalizer for Memory InterfacesJun-Yeol Lee, Hye-Ran Kim, Sanghyeon Park, Jung-Hoon Chun. 1-4 [doi]
• A 16b 1.62MS/s Calibration-free SAR ADC with 86.6dB SNDR utilizing DAC Mismatch Cancellation Based on SymmetryShota Konno, Yuichi Miyahara, Kazuki Sobue, Koichi Hamashita. 1-2 [doi]
• A Time-Domain Computing-in-Memory based Processor using Predictable Decomposed Convolution for Arbitrary Quantized DNNsJianxun Yang, Yuyao Kong, Zhao Zhang, Zhuangzhi Liu, Jing Zhou, Yiqi Wang, Yonggang Liu, Chenfu Guo, Te Hu, Congcong Li, Leibo Liu, Jin Zhang, Shaojun Wei, Jun Yang, Shouyi Yin. 1-4 [doi]
• A Monolithically Integrated Optical Bandpass Receiver in 0.25µm SiGe BiCMOS Technology for Microwave-Photonic ApplicationsGiannino Dziallas, Adel Fatemi, Falk Korndörfer, Anna Peczek, Dietmar Kissinger, Lars Zimmermann, Andrea Malignaggi, Gerhard Kahmen. 1-4 [doi]
• A 5 dBm 30.6% Efficiency 915 MHz Transmitter with $210\ \mu \mathrm{W}$ ULP PLL Employing Frequency Tripler and Digitally Controlled Duty/Phase Calibration BufferKyung-Sik Choi, Keun-Mok Kim, Jinho Ko, Sang-Gug Lee. 1-4 [doi]
• A 8-channel Rectifier-Free SECE Circuit with 15nA/ch Quescient Current and 580% Efficiency Improvement for Ambient Vibration Energy Harvesting with Broadband MEMS PET ArrayJianming Zhao, Yuan Gao, Beibei Han, Minh Sang Nguyen, Zhipeng Ding, Peter Hyun Kee Chang. 1-2 [doi]
• A 0.5-to-1.2V, 310nA Quiescent Current, 3fs-FoM Time-Domain Output-Capacitorless LDO with Propagation-Delay-Triggered Edge DetectorJianming Zhao, Yuan Gao. 1-2 [doi]
• Wireless Charging EEG Monitoring SoC with AI Algorithm-driven Electrical and Optogenetic Stimulation for Epilepsy ControlZhan-Xian Liao, Yao-Tse Chang, Chieh Tsou, Po-Hao Cheng, Hao-Yun Lee, Peng-Wei Huang, Shuenn-Yuh Lee, Chou-Ching K. Lin, Gia-Shing Shieh. 1-2 [doi]
• An Energy-Efficient GAN Accelerator with On-chip Training for Domain Specific OptimizationSoyeon Kim, Sanghoon Kang, Donghyeon Han, Sangyeob Kim, Sangjin Kim, Hoi-Jun Yoo. 1-4 [doi]
• A 16/64 QAM Baseband SoC for mm-Wave Transceiver with Self-Healing for FD/FI IQ Mismatch, LO Leakage and CFO/SCO/PNCHung-Chih Liu, Hsun-Wei Chan, Henry Lopez Davila, Kang-Lun Chiu, Chih-Wei Jen, Ngoc-Giang Doan, Zheng-Chun Huang, Hsin-Ting Chang, Nien-Hsiang Chang, Pei-Yun Tsai, Yen-Cheng Kuan, Shyh-Jye Jou. 1-2 [doi]
• A 2.68mW/Gbps, 1.62-8.1Gb/s Receiver for Embedded DisplayPort Version1.4b to Support 14dB Channel LossGunjan Mandal, Sunil Rajan, Sanjeeb Kumar Ghosh, Saikat Hazra, Raghavendra Molthati, Parin Rajnikant Bhuta, Santosh Kumar Reddy, Vishnu Kalyanamahadevi Gopalan Jawarlal, Sumanth Chakkirala, Avneesh Singh Verma, Umamaheswara Reddy Katta, Venugopal Sadana, Dayakar Bethi, Abul Hassan Savanur, Praveen S. Bharadwaj, Krupal Jitendra Mehta, Kuntal Pandya. 1-4 [doi]
• 0.5V 4.8 pJ/SOP 0.93\mu \mathrm{W}$ Leakage/core Neuromorphic Processor with Asynchronous NoC and Reconfigurable LIF NeuronVishnu P. Nambiar, J. Pu, Y. K. Lee, A. Mani, T. Luo, L. Yang, E. K. Koh, M. M. Wong, F. Li, Wang Ling Goh, A. T. Do. 1-4 [doi]
• A 12.1 TOPS/W Mixed-precision Quantized Deep Convolutional Neural Network Accelerator for Low Power on Edge / Endpoint DeviceTakanori Isono, Makoto Yamakura, Satoshi Shimaya, Isao Kawamoto, Nobuhiro Tsuboi, Masaaki Mineo, Wataru Nakajima, Kenichi Ishida, Shin Sasaki, Toshio Higuchi, Masahiro Hoshaku, Daisuke Murakami, Toshifumi Iwasaki, Hiroshi Hirai. 1-4 [doi]