A 5 dBm 30.6% Efficiency 915 MHz Transmitter with $210\ \mu \mathrm{W}$ ULP PLL Employing Frequency Tripler and Digitally Controlled Duty/Phase Calibration Buffer - researchr publication

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Kyung-Sik Choi, Keun-Mok Kim, Jinho Ko, Sang-Gug Lee. A 5 dBm 30.6% Efficiency 915 MHz Transmitter with $210\ \mu \mathrm{W}$ ULP PLL Employing Frequency Tripler and Digitally Controlled Duty/Phase Calibration Buffer. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2020, Virtual Event, Japan, November 9-11, 2020. pages 1-4, IEEE, 2020. [doi]

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