A 5 dBm 30.6% Efficiency 915 MHz Transmitter with $210\ \mu \mathrm{W}$ ULP PLL Employing Frequency Tripler and Digitally Controlled Duty/Phase Calibration Buffer - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Kyung-Sik Choi, Keun-Mok Kim, Jinho Ko, Sang-Gug Lee. A 5 dBm 30.6% Efficiency 915 MHz Transmitter with $210\ \mu \mathrm{W}$ ULP PLL Employing Frequency Tripler and Digitally Controlled Duty/Phase Calibration Buffer. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2020, Virtual Event, Japan, November 9-11, 2020. pages 1-4, IEEE, 2020. [doi]

This author has not been identified. Look up 'Kyung-Sik Choi' in GoogleThis author has not been identified. Look up 'Keun-Mok Kim' in GoogleThis author has not been identified. Look up 'Jinho Ko' in GoogleThis author has not been identified. Look up 'Sang-Gug Lee' in Google

runs on WebDSL