Kyung-Sik Choi, Keun-Mok Kim, Jinho Ko, Sang-Gug Lee. A 5 dBm 30.6% Efficiency 915 MHz Transmitter with $210\ \mu \mathrm{W}$ ULP PLL Employing Frequency Tripler and Digitally Controlled Duty/Phase Calibration Buffer. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2020, Virtual Event, Japan, November 9-11, 2020. pages 1-4, IEEE, 2020. [doi]
@inproceedings{ChoiKKL20,
title = {A 5 dBm 30.6% Efficiency 915 MHz Transmitter with $210\ \mu \mathrm{W}$ ULP PLL Employing Frequency Tripler and Digitally Controlled Duty/Phase Calibration Buffer},
author = {Kyung-Sik Choi and Keun-Mok Kim and Jinho Ko and Sang-Gug Lee},
year = {2020},
doi = {10.1109/A-SSCC48613.2020.9336141},
url = {https://doi.org/10.1109/A-SSCC48613.2020.9336141},
researchr = {https://researchr.org/publication/ChoiKKL20},
cites = {0},
citedby = {0},
pages = {1-4},
booktitle = {IEEE Asian Solid-State Circuits Conference, A-SSCC 2020, Virtual Event, Japan, November 9-11, 2020},
publisher = {IEEE},
isbn = {978-1-7281-8436-4},
}