Table of Contents

• A Crystal-Less Clock Generator for Low-Power and Low-Cost Sensor Transceivers with 12.9MHz-to-3.3GHz Range, 16.67ppm/°C Inaccuracy from -25°C to 85°C, and 0.25us Settle-TimeSangdon Jung, Jehyeok Yu, Minsu Park, Jung-Hoon Chun. 1-3 [doi]
• A 6.78-MHz Wireless Power Transfer System with Voltage-/Current-Mode 0X/1X Regulating Rectifier and Global-Loop Power ControlBing-Jen Wu, Dao-Han Yao, Po-Hung Chen. 1-3 [doi]
• A Triple-Band Radio for WLAN 11b/g/n/ax in 45nm CMOSDebapriya Sahu, V. Srinivas, Rohit Chatterjee, Meghna Agarwal, P. Agrawal, R. Juluri, M. Mukherjee, Vimal Edayath, A. Yerramsetty, G. Bakalzuk, O. Rahmanony, K. RajMohan, A Sancheti, R. Anand. 1-3 [doi]
• A 4ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3Jinook Jung, Jun-Han Choi, Kyoung-Jun Roh, Jaewoo Park, Won-Mook Lim, Tae Sung Kim, Han-Ki Jeong, Myoungbo Kwak, Jaeyoun Youn, Jeong-Don Ihm, Changsik Yoo, Youngdon Choi, Jung Hwan Choi, Hyungjong Ko. 1-3 [doi]
• A D-Band ASK Transmitter with 50GHz RF Bandwidth and Multi-Mode Interface Implemented in 28nm CMOSRui Zhang, Dawei Tang, Zhe Chen, Liqun Lu, Peigen Zhou, Jixin Chen, Wei Hong 0002. 1-3 [doi]
• 248 GHz Compact Mixer-Last Direct-Conversion Transmitter with I/Q Imbalance and LO Feedthrough Calibration CapabilitySeunghoon Lee, Junhyeong Kim, Ho-Jin Song. 1-3 [doi]
• A Wideband Low-Noise Linear LiDAR Analog Front-End Achieving 1.6 GHz Bandwidth, $\boldsymbol{2.7}\ \mathbf{pA}/\mathbf{Hz}^{\boldsymbol{0.5}}$ Input Referred Noise, and 103 $\mathbf{dB}\mathbf{\Omega}$ Transimpedance GainYidan Zhang, Zhao Zhang 0004, Yiqing Xu, Xinyu Shen, Nan Qi, Nanjian Wu, Jian Liu 0021, Liyuan Liu. 1-3 [doi]
• A 28nm 49.7TOPS/W Sparse Transformer Processor with Random-Projection-Based Speculation, Multi-Stationary Dataflow, and Redundant Partial Product EliminationYubin Qin, Yang Wang 0089, Dazheng Deng, Xiaolong Yang, Zhiren Zhao, Yang Zhou, Yuanqi Fan, Jingchuan Wei, Tianbao Chen, Leibo Liu, Shaojun Wei, Yang Hu 0001, Shouyi Yin. 1-3 [doi]
• A 2pA/√Hz Current-Conveyor-Assisted Ultrasound Receiver with 25pF CMUT Parasitic CapacitanceGichan Yun, Kyeongwon Jeong, Haidam Choi, Seunghyeon Nam, Chaerin Oh, Hyunjoo Jenny Lee, Sohmyung Ha, Minkyu Je. 1-3 [doi]
• An 80-dB Dynamic Range Hybrid Pulse-Phase Analog Front-End Circuit Cooperating With a Low-Resolution TDC for LiDARZeli Li, Tianrui Lyu, Kaiyou Li, Haoxin Zheng, Zhuohang Ye, Shengzhao Su, Jianping Guo, Yang Liu. 1-3 [doi]
• Flexible and Efficient Implementation of CRYSTALS-KYBER SIMD RISC-V Coprocessor Based on Customized Vector Instruction-Set ExtensionJiaming Zhang, Jiahao Lu, Dongsheng Liu, Aobo Li, Xiang Li, Shuo Yang, Ang Hu, Xuecheng Zou. 1-3 [doi]
• A 2D Beam-Steerable 252-285-GHz 25.8-Gbit/s CMOS Receiver ModuleTakeshi Yoshida, Shinsuke Hara, Tatsuo Hagino, Mohamed H. Mubarak, Akifumi Kasamatsu, Kyoya Takano, Yoshiki Sugimoto, Kunio Sakakibara, Shuhei Amakawa, Minoru Fujishima. 1-3 [doi]
• CIMFormer: A 38.9TOPS/W-8b Systolic CIM-Array Based Transformer Processor with Token-Slimmed Attention Reformulating and Principal Possibility GatheringRuiqi Guo, Yang Wang, Xiaofeng Chen, Lei Wang, Hao Sun, Jingchuan Wei, Leibo Liu, Shaojun Wei, Yang Hu 0001, Shouyi Yin. 1-3 [doi]
• A Jitter-Programmable Bang-Bang Phase-Locked Loop Using PVT Invariant Stochastic Jitter MonitorYongjo Kim, Taekwang Jang, SeongHwan Cho. 1-3 [doi]
• A Fully Integrated Bit-to-Bit 24/48Gb/s QPSK/16-QAM D-Band Transceiver with Mixed-Signal Baseband in 28nm CMOS TechnologyPingda Guan, Haikun Jia, Wei Deng 0001, Ruichang Ma, Mingxing Deng, Jiamin Xue, Angxiao Yan, Shiyan Sun, Zhihua Wang 0001, Baoyong Chi. 1-3 [doi]
• ForewordKen Takeuchi. 1-2 [doi]
• K/Ka-Band 4-Element 4-Beam Hybrid Phased-Array Transmitter and Receiver Front-Ends with Compact Layout Floor-Plans and Fault-Tolerant Digital CircuitsMengru Yang, Chenyu Xu, Peng Gu, Yongran Yi, Mohan Guo, Liangliang Liu, Xiangxi Yan, Xiaohu You 0001, Dixian Zhao. 1-3 [doi]
• A 71-to-86GHz, 20.4dBm $\mathbf{P}_{\mathbf{out}}$, 6.0dB NF Transceiver with Quadrature Direct-Modulated Transmitter and Reflection-Less Heterodyne Receiver in 40nm CMOSJie Zhou 0026, Changxuan Han, Wen Chen, Bingzheng Yang, Xun Luo. 1-3 [doi]
• A 1.2 V 2.3 µW 94.7 dB DR Delta-Sigma Modulator With Dynamic-Range Enhancement and Tri-Level CDACCong Wei, Rongshan Wei, Lijie Huang, Gongxing Huang, Jinze Lai, Zhichao Tan. 1-3 [doi]
• LOG-CIM: A 116.4 TOPS/W Digital Computing-In-Memory Processor Supporting a Wide Range of Logarithmic Quantization with Zero-Aware 6T Dual-WL CellSoyeon Um, Sangjin Kim, Seongyon Hong, Sangyeob Kim, Hoi-Jun Yoo. 1-3 [doi]
• 3D-ISC: A 65nm 3D Compatible In-Sensor Computing Accelerator with Reconfigurable Tile Architecture for Real-Time DVS Data CompressionGokul Krishnan, Gopikrishnan Raveendran Nair, Jonghyun Oh, Anupreetham Anupreetham, Pragnya Sudershan Nalla, Ahmed Hassan, Injune Yeo, Kishore Kasichainula, Jae-sun Seo, Mingoo Seok, Yu Cao. 1-3 [doi]
• A Primary Driver with Real-Time Resonance Tracking for Wireless-Powered Implantable Medical DevicesXiaodong Meng, Xing Li 0004, Yuan Yao, Chi-Ying Tsui, Wing-Hung Ki. 1-3 [doi]
• A Ka-Band Mutual Coupling Resilient Balanced PA with Magnetic Coupling Self-Cancelling Inductor Achieving 21.2dBm OP1dBand 27.6% PAE1dBJian Zhang, Wei Zhu, Dawei Wang, Xiangjie Yi, Ruitao Wang, Yan Wang. 1-3 [doi]
• rd-Order SAR-Assisted CT DSM with 1-0 MASH and DNCKent Edrian Lozada, Dong-Hun Lee, Ye-Dam Kim, Ho-Jin Kim, Youngjae Cho, Michael Choi, Seung-Tak Ryu. 1-3 [doi]
• A 2 x 24Gb/s Single-Ended Transceiver with Channel-Independent Encoder-Based Crosstalk Cancellation in 28nm CMOSHongzhi Wu, Weitao Wu, Liping Zhong, Xuxu Cheng, Xiongshi Luo, Zhenghao Li, Dongfan Xu, Quan Pan 0002. 1-3 [doi]
• A 5.2GHz Trifilar Transformer-Based Class-F23 Noise Circulating VCO with FoM of 192.6 dBc/HzHanzhang Cao, Tongde Huang, Xiaolong Liu, Hao Wang, Jin Jin, Wen Wu. 1-3 [doi]
• 2 27μJ/image Digital Edge Neuromorphic Chip with On-Chip 802 Frame/s Multi-Layer Spiking Neural Network LearningTengxiao Wang, Min Tian, Zhengqing Zhong, Haibing Wang, Junxian He, Fang Tang, Xichuan Zhou, Shuangming Yu, Nanjian Wu, Liyuan Liu, Cong Shi 0003. 1-3 [doi]
• An Area and Power Efficient Fully Nonlinear 10-bit Column Driver with Time-Shared Multi-Gamma-Slope DAC and Time-Interleaved Sampling Buffer for Mobile AMOLEDsSeung Hun Choi, Jeongmin Kim, Jaewoong Ahn, Junyeol An, JiWoong Kim, Ohjo Kwon, Ki-Duk Kim, Hyung-Min Lee. 1-3 [doi]
• A Resource-Efficient Super-Resolution FPGA Processor with Heterogeneous CNN and SNN Core ArchitectureJiwon Choi, Sangyeob Kim, Wonhoon Park, Wooyoung Jo, Hoi-Jun Yoo. 1-3 [doi]
• An Energy-Efficient Heterogeneous Fourier Transform-Based Transformer Accelerator with Frequency-Wise Dynamic Bit-PrecisionJingu Lee, Sangjin Kim, Wooyoung Jo, Hoi-Jun Yoo. 1-3 [doi]
• A 0.5-to-1.5GHz BW-Extended Gain-Boosted N-Path Filter Using a Switched $\mathbf{g}_{\mathbf{m}}-\mathbf{C}$ Network Achieving 50MHz BW and 18.2dBm OB-IIP3Gengzhen Qi, Pui-In Mak. 1-3 [doi]
• A 10TFLOPS Datacenter-Oriented GPU with 4-Corner Stacked 64GB Memory by The Means of 2.5D Packaging TechnologyShuang Wang, Weiliang Chen, Xueqing Li, Leibo Liu, Huazhong Yang. 1-3 [doi]
• A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power ApplicationsHyun-A. Ahn, Yoo-Chang Sung, Yong Hun Kim, Janghoo Kim, Kihan Kim, Donghun Lee, Young-Gil Go, Jae-Woo Lee, Jae-Woo Jung, Yong-Hyun Kim, Garam Choi, Jun Seo Park, Bo-Hyeon Lee, Jin-Hyeok Baek, Daesik Moon, Daihyun Lim, Seung-Jun Bae, Young-Soo Sohn, Changsik Yoo, Tae-young Oh. 1-4 [doi]
• A 1.08ms Ultrafast Scanning Capacitive Touch-Screen Sensor Interface with Charge-Interpolated Common-Mode Compensation and Host-Based Adaptive Median FilteringJonghang Choi, Subin Kim, Yongjun Lee, Sanghyun Heo, Keum-Dong Jung, Young Ha Hwang, Jun-Eun Park. 1-3 [doi]
• A Wide Frequency Range, Small Area and Low Supply Memory Interface PLL Using a Process and Temperature Variation Aware Current Reference in 3 nm Gate-All Around CMOSKyungmin Lee, Jaehong Jung, Gyusik Kim, Joomyoung Kim, Seungjin Kim, Seunghyun Oh, Sung-Min Park 0001, Jongwoo Lee. 1-3 [doi]
• IEEE ASSCC 2023/ Session 10/ Paper 10.5Ruichang Ma, Haikun Jia, Hongzhuo Liu, Wei Deng 0001, Zhihua Wang 0001, Baoyong Chi. 1-3 [doi]
• 5G Lessons Learned and an Outlook on 6GBongtae Kim. 1-2 [doi]
• MSN: Battery-Less Multiple Subcarrier Multiple Access Sensor Node with Full-Duplex Backscatter Concurrent Data StreamingYuxiao Zhao, Hanyang Wang, Yongming Xu, Zhongyuan Ying, Yu Lu, Jinlin Liu, Tuo Hu, Jin Mitsugi, Hao Min. 1-3 [doi]
• A 5GS/s 38.04dB SNDR Single-Channel TDC-Assisted Hybrid ADC with $\lambda/4$ Transmission Line Based Time Quantizer Achieving a PVT Robustness 416.6fs Time StepHongzhi Liang, Yi Shen 0007, Jun Chang, Shubin Liu, Ruixue Ding, Zhangming Zhu. 1-3 [doi]
• A $\mathbf{160}\times \mathbf{120}$ Indirect Time-of-Flight Sensor with Pixel-Level Adaptive $\Delta\Sigma$-Operations for Background Light CancellationYongjae Park, Jubin Kang, Dahwan Park, Insang Son, Jung-Hye Hwang, Seong-Jin Kim. 1-3 [doi]
• An On-Chip DC-DC Converter and Power Management System Achieving Zero Standby-to-Active Transition Time in MCUToyohiro Shimogawa, Makoto Nonaka, Toma Ogata, Toshiki Kiryu, Yasuto Igarashi, Kosuke Yayama, Masahiro Kitamura, Hiromichi Ishikura, Mitsuru Hiraki, Masao Ito, Takashi Kono. 1-3 [doi]
• A 40nm $\boldsymbol{2.76}\boldsymbol{\mu}\mathbf{J}/\mathbf{Op}$ Energy-Efficient Secure Post-Quantum Crypto-Processor for Crystals-Kyber on Module-LWEAobo Li, Jiahao Lu, Dongsheng Liu, Xiang Li, Shuo Yang, Tianze Huang, Jiaming Zhang, Siqi Xiong, Chenjun Yang. 1-3 [doi]
• An Adaptive-Sampling Digital LDO with Statistical Comparator Selection Achieving 99.99% Maximum Current Efficiency and 0.25ps FoM in 65nmShun Yamaguchi, Takashi Hisakado, Osami Wada, Mahfuzul Islam 0001. 1-3 [doi]
• A 110-160 GHz ASK Receiver with Isomorphic Low Noise Power Amplifier and Multi-Mode Interface in 28-nm CMOSDawei Tang, Zekun Li 0005, Leyang Huang, Rui Zhang, Liqun Lu, Chun Yang, Zheng Yan, Peigen Zhou, Zhe Chen, Jixin Chen, Wei Hong 0002. 1-3 [doi]
• An 11bit 360MS/s Pipelined SAR ADC with Dynamic Negative-C Assisted Residue AmplifierYigi Kwon, Sangwoo Lee, Changuk Lee, Hyunchul Yoon, Byounghan Min, Youngcheol Chae. 1-3 [doi]
• A 33.6 FPS Embedding based Real-time Neural Rendering Accelerator with Switchable Computation Skipping Architecture on Edge DeviceJongjun Park, Donghyeon Han, Junha Ryu, Dongseok Im, Gwangtae Park, Hoi-Jun Yoo. 1-3 [doi]
• A Transient Enhancement Digital LDO with Adaptive Ripple Cancelation Based on Optimal Compensation Period ApproximationAngxiao Yan, Wei Deng 0001, Haikun Jia, Shiwei Zhang, Baoyong Chi. 1-3 [doi]
• Integrated Circuit to Compensate Parasitic Leakage Component for WL Leakage Current in NAND Flash MemoryBu-Il Nam, Jayang Yoon, Kyunghea Lee, Sol Kim, Junhong Park, Chiweon Yoon, Eunkyoung Kim. 1-3 [doi]
• A DRAM Bandwidth-Scalable Sparse Matrix-Vector Multiplication Accelerator with 89% Bandwidth Utilization Efficiency for Large Sparse MatrixHyunJi Kim, Eunkyung Ham, Sunyoung Park, Hana Kim, Ji-Hoon Kim. 1-3 [doi]
• A PAM4 Level Mismatch Adjustment Scheme for 48-Gb/s PAM4 Memory Tester BridgeDaeho Yun, Minsu Park, Kahyun Kim, Kyungmin Baek, Eonhui Lee, Woo-seok Choi, Deog Kyoon Jeong. 1-3 [doi]
• An $8.73\mathrm{G}\Omega$ Input Impedance VCO-Based Neural Front-End with Autonomous Time-Domain Impedance Boosting Technique and Maximum 0.215s Re-Calibration TimeHuaiyu Liu, Yang Lin, Guoxing Wang, Yan Liu 0016. 1-3 [doi]
• An 18-nW, 170°C Temperature Range, Voltage and Current Reference Circuit with Low Line SensitivityI-Fan Lin, Yu-Chu Tsai, Heng-Li Lin, Yu-Te Liao. 1-3 [doi]
• A 23.9 µW 13.6-bit Period Modulation-Based Capacitance-to-Digital Converter with Dynamic Current Mirror Front-end Achieving Capacitor Range of 1 to 68 pFHyeyeon Lee, Donguk Seo, Young-Jin Woo, Yoonmyung Lee, Inhee Lee, Youngcheol Chae. 1-3 [doi]
• rd-Harmonic Direct-Solution TechniqueXiangdong Feng, Xin Liu, Yangfan Xuan, Fengheng Li, Yuxuan Luo, Ping Wang, Bo Zhao 0003. 1-3 [doi]
• A 74.0 dB-SNDR 175.4 dB-FoM Pipelined-SAR ADC Using a Cyclically Charged Floating Inverter AmplifierChangjoo Park, Jeongmyeong Kim, Kyounghun Kang, Minkyu Yang, Byeongmin Moon, Siheon Lee, Wanyeong Jung. 1-3 [doi]
• An 8.5ps Resolution, $2000\mu\mathrm{m}^{2}$ Phase-Domain Delta-Sigma TDC for Lidar ApplicationsYoondeok Na, Seokho Yun, Myung-Jae Lee, Youngcheol Chae. 1-3 [doi]
• 2Jiangchao Wu, Guangshu Zhao, Litao Zhang, Yu Jia, Yang Jiang 0002, Pui-In Mak, Rui Paulo Martins, Man Kay Law. 1-3 [doi]
• TEPD: A Compound Timing Detection of Both Data-Transition and Path-Activation for Reliable In-Situ Timing Error Detection and Correction in 28nm CMOSZhengguo Shen, Junyi Qian, Keran Li, Ziyu Li, Lishuo Deng, Weiwei Shan. 1-3 [doi]
• A 73.8K Inference/mJ SVM Learning Accelerator for Brain Pattern RecognitionTzu-Wei Tong, Yi-Yen Hsieh, Tai-Jung Chen, Chia-Hsiang Yang. 1-3 [doi]
• A 226 GHz Coupled Harmonic VCO with 9.34% Tuning Range Utilizing Three-Coil Transformer with Switched Inductor in 65nm CMOSYue Liang, Qin Chen, Xu Wu, Xiangning Fan, Lianming Li. 1-3 [doi]
• ESD Protection is About Circuit Design: Practices and PerspectivesWeiquan Hao, Xunyu Li, Zijin Pan, Runyu Miao, Albert Z. Wang. 1-3 [doi]
• A Resistor/Trimming-Less Self-Biased Current Reference Class with Area Down to $3,500\ \mu \mathrm{m}^{2}$, 42.8 pW Power and 10.4% Accuracy across Corner Wafers in 180 nmLuigi Fassio, Hoang Hong Hanh, Massimo Alioto. 1-3 [doi]
• A Low Noise 8Mpixel CMOS Image Sensor with 5.36GHz Global Counter and Dual Latch Skew Canceler for Surveillance AI Camera SystemYoichi Iizuka, Akihide Maezono, Wataru Saito, Atsushi Yamane, Kazuhiko Takami, Fukashi Morishita. 1-3 [doi]
• A 28nm 386.5GOPS/W Coarse-Grained DSP Using Configurable Processing Elements for Always-on Computation with FPGA ImplementationHedi Wang, Zengwei Wang, Yaolei Li, Chen Tang, Jinxu Gao, Huazhong Yang, Yongpan Liu. 1-3 [doi]
• A Time-Based PAM-4 Transceiver Using Single Path Decoder and Fast-Stochastic Calibration TechniquesDong Hyun Yoon, He Junsen, Kwang-Hyun Baek, Youngdon Choi, Jung Hwan Choi, Tony Tae-Hyoung Kim. 1-3 [doi]
• A Hybrid Integrated W-Band 4-Element Phased-Array Transceiver Front-End Achieving 21.6% Full TX Peak PAE at 14.8dBm Output Power and <1°/dB Phase/Gain Resolution in 65-nm CMOS TechnologyWei Zhu, Jian Zhang, Jiazhi Ying, Xiangjie Yi, Yan Wang, Houjun Sun. 1-3 [doi]
• A 12.75-to-16-GHz Spur-Jitter-Joint-Optimization SS-PLL Achieving -94.55-dBc Reference Spur, 31.9-fs Integrated Jitter and -260.1-dB FoMYixi Li, Zhao Zhang 0004, Yong Chen 0005, Xinyu Shen, Zhao Zhang, Nan Qi, Jian Liu 0021, Nanjian Wu, Liyuan Liu. 1-3 [doi]
• An $890\quad \mu\mathrm{W}$ Multichannel Injection-Locked OOK Transmitter with 23% Global Efficiency and 22 pJ/bit Energy EfficiencySheng-Kai Chang, Shao-Ting Chang, Zhi-Wei Lin, Kuang-Wei Cheng. 1-3 [doi]
• A 28-nW Noise-Robust Voice Activity Detector with Background Aware Feature ExtractionJingsen Yang, Liangjian Lyu, Zirui Dong, Heyu Ren, C.-J. Richard Shi. 1-3 [doi]
• A $142.8-\mu \text{W}$ 98.1dB-SNDR Power/Bandwidth Configurable Fully Dynamic Discrete-Time Zoom ADC with Interstage Leakage ShapingYuke Shen, Shubin Liu, Kui Wen, Yanbo Zhang, Yi Shen 0007, Ruixue Ding, Zhangming Zhu. 1-3 [doi]
• 2-20-V Wide Input Range Active Rectifier with Single-Multiplexing Adaptive Delay Compensation and Low-Voltage Enhancement for Wireless Power TransmissionChao Xie, Guangshu Zhao, Junliang Wei, Man Kay Law, Milin Zhang. 1-3 [doi]
• SESOMP: A Scalable and Energy-Efficient Self-Organizing Map Processor with Computing-In-Memory and Dead Neuron PruningYuncheng Lu, Xin Zhang, Zehao Li, Bo Wang 0020, Tony Tae-Hyoung Kim. 1-3 [doi]
• Task-Specific Low-Power Beamforming MIMO Receiver Using 2-Bit Analog-to-Digital ConvertersTimur Zirtiloglu, Peter Crary, Eyyup Tasci, Arslan Riaz, Yonina C. Eldar, Nir Shlezinger, Rabia Tugce Yazicigil. 1-3 [doi]
• nd-Order Nonlinearity Error ShapingYanbo Zhang, Xianghui Zhang, Li Tian, Shubin Liu, Zhangming Zhu. 1-3 [doi]
• A Cryo-CMOS 4.5~7GHz Dual-Qubit Homodyne Reflectometer Array with High Q Degenerate Parametric Amplifier Through Dynamic Mode CouplingYujie Geng, Haichuan Lin, Bo Wang, Cheng Wang. 1-2 [doi]
• 2 Single-Channel 1 GS/s 8-Bit 3-Stage Capacitor Array-Assisted Charge-Injection DAC-Based SAR ADC in 28 nm CMOSChan-Ho Kye, Kyojin Choo. 1-3 [doi]
• An Instant-Setup On-Delay Compensation Scheme Based on Phase Detection for Series-Resonant Wireless Power Receiver with Up-to-4.41% Efficiency EnhancementYuxuan Luo, Yutang Chen, Jianping Guo, Xian Tang, Dihu Chen. 1-3 [doi]
• GCFP-ACIM: A 40nm 4.74TFLOPS/W General Complex Float-Point Analog Compute-in-Memory with Adaptive Power-Saving for HDR Signal Processing ApplicationsZizhao Ma, Xianwu Hu, Gan Wen, Yihao Wang, Zeming Wang, Yukai Lin, Yu Wang, Yuhao Guo, Yanlei Li, Xingdong Liang, Xiaoyang Zeng, Yufeng Xie. 1-3 [doi]
• A 54-to-69-GHz Wideband 2T2R FMCW Radar Transceiver Employing Cascaded-PLL Topology and PTAT-Enhanced Temperature Compensation in 40-nm CMOSChenyu Xu, Xiaofei Liao, Feifan Hong, Mengru Yang, Peijuan Ju, Wendi Chen, Pengfei Diao, Hao Gong, Xiang Liu, Xiaohu You 0001, Dixian Zhao. 1-3 [doi]
• A 27-to-31.6 GHz 8-Element Phased-Array Transmitter Front-End with Inter-Element-Interference Cancellation Scheme in 65 nm CMOSDongze Li, Wei Deng 0001, Xintao Li, Ruiheng Qiu, Haikun Jia, Xiangrong Huang, Ziyuan Guo, Baoyong Chi. 1-3 [doi]
• A 5.37-TSOPS/W Reconfigurable Neuron Array with Dual-mode Neurons and Asynchronous Synapses for Energy-Efficient Inference and Biological Neural Network SimulationXiangao Qi, Yuqing Lou, Yongfu Li 0002, Guoxing Wang, Kea-Tiong Tang, Jian Zhao 0004. 1-3 [doi]
• A 0.12-V 200-Hz-BW 10-Bit ADC Using Quad-Channel VCO and Interpolation LinearizationShea Smith, Taylor Barton, Yen-Cheng Kuan, Armin Tajalli, Mau-Chung Frank Chang, Shiuh-Hua Wood Chiang. 1-3 [doi]
• A $\boldsymbol{4} \times \boldsymbol{112}-\mathbf{Gb}/\mathbf{s}$ PAM-4 Silicon-Photonic Transceiver Front-End for Linear-Drive Co-Packaged OpticsHan Liu, Nan Qi, Donglai Lu, Zizheng Dong, Zhihan Zhang, Jian He, Guike Li, Leliang Li, Ye Liu, Ziyue Dang, Daigao Chen, Zhao Zhang 0004, Jian Liu 0021, Nanjian Wu, Xi Xiao, Liyuan Liu. 1-3 [doi]
• A 2-W, 90%-Efficiency Single-Stage Dual-Output Wireless Power Receiver with 0.1 to 700-mA Output Current Range Through Dynamic Delay Compensation and Bootstrap Adaptive Body Biasing CircuitYutang Chen, Yuxuan Luo, Jianping Guo, Xian Tang, Dihu Chen. 1-3 [doi]
• A 26.9-GHz 4-Element Code-Domain Hybrid Beamforming Phased-Array ReceiverZiyi Lin, Haikun Jia, Chuanming Zhu, Wei Deng 0001, Huabing Liao, Bao Shi, Lujie Hao, Xiangrong Huang, Baoyong Chi. 1-3 [doi]
• A Compact 1,257-Gbps/W Byte-Serial AES Accelerator for IoT Applications in 22 nmShutao Zhang, Malte Wabnitz, Tobias Gemmeke. 1-3 [doi]
• A 26-30GHz Digitally-Controlled Variable Gain Power Amplifier with Phase Compensation and Third Order Nonlinearity Cancellation TechniqueHaoqi Qin, Junjie Gu, Hao Xu, Weitian Liu, Kefeng Han, Rui Yin, Zongming Duan, Hao Gao, Na Yan. 1-3 [doi]
• A 92.7%-Efficiency 6.78-MHz Dual-Output Energy-Resuscitating Resonant Regulating Rectifier for Wirelessly Powered SystemsHyun-Su Lee, Hyung-Min Lee. 1-3 [doi]
• Welcome MessageLeibo Liu. 1-2 [doi]
• A 6.4Gbps/pin NAND Flash Memory Multi-Chip Package Employing a Frequency Multiplying Bridge Chip for Scalable Performance and Capacity Storage SystemsShinichi Ikeda, Akira Iwata, Goichi Otomo, Tomoaki Suzuki, Hiroaki Iijima, Mikio Shiraishi, Shinya Kawakami, Masatomo Eimitsu, Yoshiki Matsuoka, Kiyohito Sato, Shigehiro Tsuchiya, Yoshinori Shigeta, Takuma Aoyama. 1-3 [doi]
• Semiconductor Chip Design in a LegolandChih-Ming Hung. 1-4 [doi]
• A 4-Element 4-Beam Ka-Band Phased-Array Receiver Using Mesh Topology in 65 nm CMOSXiangrong Huang, Haikun Jia, Wei Deng 0001, Chuanming Zhu, Zhihua Wang 0001, Xuzhi Liu, Zhiming Chen 0001, Baoyong Chi. 1-3 [doi]
• 2 Peak Current DensityQiaobo Ma, Huihua Li, Xiongjie Zhang, Anyang Zhao, Yang Jiang 0002, Man Kay Law, Rui Paulo Martins, Pui-In Mak. 1-3 [doi]
• A 80Gb/s/pin Single-Ended PAM-4 Transmitter With an Edge Boosting Auxiliary Driver and a 4-Tap FFE in 28-nm CMOSDaewon Rho, Jae-Koo Park, Seung-Jae Yang, Woo-Young Choi. 1-3 [doi]
• A 400MHz 249.1TOPS/W 64Kb Fully-Reconfigurable SRAM-Based Digital Compute-in-Memory Macro for Accelerating CNNsXin Zhang, Vishal Sharma, Yuncheng Lu, Yong-Jun Jo, Tony Tae-Hyoung Kim. 1-3 [doi]
• A Low-Voltage Bias-Current-Free Pseudo-Differential Hybrid PLL Using a Time-Interleaving Flip-Flop Phase DetectorLiqun Feng, Qianxian Liao, Woogeun Rhee, Zhihua Wang 0001. 1-3 [doi]
• A 200MHz Bandwidth 84% Peak Efficiency AC-Coupled Envelope Tracking Supply Modulator with 10MHz Constant Switching FrequencyPeng Xu, Xueli Zhang, Tao Wang, Peng Cao, Jiawei Xu 0001, Zhiliang Hong. 1-3 [doi]
• A Compact E-Band Load-Modulation Balanced Power Amplifier Using Coupled Transmission-Line Output Network Achieving 22.1-dBm Psat and 34.9%/12.2% Efficiency at Psat/6-dB PBOXiangrong Huang, Haikun Jia, Wei Deng 0001, Zhihua Wang 0001, Baoyong Chi. 1-3 [doi]
• Architecture Challenges for Heterogeneous Processors in Embedded SoCsMasayuki Ito. 1-2 [doi]