Table of Contents

• A 12.4TOPS/W, 20% Less Gate Count Bidirectional Phase Domain MAC Circuit for DNN Inference ApplicationsYosuke Toyama, Kentaro Yoshioka, Koichiro Ban, Akihide Sai, Kohei Onizuka. 1-4 [doi]
• Circuit Design in Nano-Scale CMOS TechnologiesKevin Zhang. 1-4 [doi]
• Ultra-Lightweight 548-1080 Gate 166Gbps/W-12.6Tbps/W SIMON 32/64 Cipher Accelerators for IoT in 14nm Tri-gate CMOSHimanshu Kaul, Mark Anders, Sanu Mathew, Vikram Suresh, Sudhir Satpathy, Amit Agarwal, Steven Hsu, Ram Krishnamurthy. 1-4 [doi]
• A 0.46V-1.1V Transition-Detector with In-Situ Timing-Error Detection and Correction Based on Pulsed-Latch Design in AES AcceleratorXinchao Shang, Weiwei Shan, Jiaming Xu, Minyi Lu, Yiming Xiang, Longxing Shi, Jun Yang. 1-4 [doi]
• An 11b 1GS/s Time-Interleaved ADC with Linearity Enhanced T/HYan Zhu 0001, Chi-Hang Chan, Rui Paulo Martins. 1-2 [doi]
• An Ultra-low Power 8T SRAM with Vertical Read Word Line and Data Aware Write AssistLu Lu, Taegeun Yoo, Van Loi Le, Tony Tae-Hyoung Kim. 1-2 [doi]
• A Power and Area Efficient 2.5-16 Gbps Gen4 PCIe PHY in 10nm FinFET CMOSShenggao Li, Fulvio Spagna, Ji Chen, Xiaoqing Wang, Luke Tong, Sujatha Gowder, Wenyan Jia, Roan Nicholson, Sitaraman Iyer, Rui Song, Lily Li, Meng-Hung Chen, Amanda Tran, Michael De Vita, Deepar Govindrajan, Marcus Pasquarella, Dave Bradley, Frank Verdico, Matt Duwe, Eric Lee, Michelle Wigton. 5-8 [doi]
• Open the New World of 5GSeizo Onoe. 5-8 [doi]
• 40-nm 64-kbit Buffer/Backup SRAM with 330 nW Standby Power at 65°C Using 3.3 V IO MOSs for PMIC less MCU in IoT ApplicationsYoshisato Yokoyama, Tomohiro Miura, Yukari Ouchi, Daisuke Nakamura, Jiro Ishikawa, Shunya Nagata, Makoto Yabuuchi, Yuichiro Ishii, Koji Nii. 9-12 [doi]
• Practical Challenges in Supporting Function in MemoryNam Sung Kim. 9-12 [doi]
• AI Drives Domain Specific ProcessorsYi Kang. 13-16 [doi]
• Logic Process Compatible 40nm 256K×144 Embedded RRAM with Low Voltage Current Limiter and Ambient Compensation Scheme to Improve the Read WindowChien-An Lai, Chung-Cheng Chou, Chi-Hsiang Weng, Zheng-Jun Lin, Pei-Ling Tseng, Chien-Fan Wang, Chih-Chen Wang, Chin-I Su, Wei-Chi Chen, Yu-Cheng Lin, Tong-Chern Ong, Chi Chang, Yu-Der Chih, Tsung-Yung Jonathan Chang. 13-16 [doi]
• A 10-Bit 1026-Channel Column Driver IC with Partially Segmented Piecewise Linear Digital-to-Analog Converters for Ultra-High-Definition TFT-LCDs with One Billion Color DisplayChih-Wen Lu, You-Gang Chang, Xing-Wei Huang, Jhih-Siou Cheng, Po-Yu Tseng, Chih-Hsien Chou. 17-20 [doi]
• A WDR CMOS Image Sensor Employing In-pixel Capacitive Variation using a Re-configurable Source Follower for Low Light ApplicationsNeha Priyadarshini, Chandani Anand, Mukul Sarkar. 21-24 [doi]
• A CMOS Imager for Reflective Pulse Oximeter with Motion Artifact and Ambient Interference RejectionsHsiang-Lin Chen, Sung-En Hsieh, Tzu-Hsiang Hsu, Chih-Cheng Hsieh. 25-26 [doi]
• 2 Orthogonal Sampling-Based Parallel Neural Recording SystemReza Ranjandish, Alexandre Schmid. 27-30 [doi]
• An Integrated DC-DC Converter with Segmented Frequency Modulation and Multiphase Co-Work Control for Fast Transient RecoveryU. Fat Chio, Kuo-Chih Wen, Sai-Weng Sin, Chi-Seng Lam, Yan Lu, Franco Maloberti, Rui Paulo Martins. 31-32 [doi]
• An 88% Efficiency 2.4μW to 15.6μW Triboelectric Nanogenerator Energy Harvesting System Based on a Single-Comparator Control AlgorithmKarim Rawy, Ruchi Sharma, Hong Joon Yoon, Usman Khan, Sang-Woo Kim, Tony T. Kim. 33-36 [doi]
• A Wide-Range Capacitive DC-DC Converter with 2D-MPPT for Soil/Solar Energy ExtractionI-Che Ou, Jia-Ping Yang, Chia-Hung Liu, Kai-Jie Huang, Kun-Ju Tsai, Yu Lee, Yuan-Hua Chu, Yu-Te Liao. 37-38 [doi]
• A 13.56 MHz 88.7%-PCE Voltage Doubling Rectifier Using Adaptive Delay Time and Pulse-Width ControlYe-Sing Luo, Hsing-Hung Lin, Shen-Iuan Liu. 39-42 [doi]
• 2 Resistor-Based Temperature Sensor in 180-nm CMOSJan Angevare, Kofi A. A. Makinwa. 43-46 [doi]
• FPGA-based CNN Processor with Filter-Wise-Optimized Bit PrecisionAsuka Maki, Daisuke Miyashita, Kengo Nakata, Fumihiko Tachibana, Tomoya Suzuki, Jun Deguchi. 47-50 [doi]
• An Asynchronous Energy-Efficient CNN Accelerator with Reconfigurable ArchitectureWeijia Chen, Hui Wu, Shaojun Wei, Anping He, Hong Chen. 51-54 [doi]
• Hardware Architecture for Fast General Object Detection using Aggregated Channel FeaturesKoichi Mitsunari, Jaehoon Yu, Masanori Hashimoto. 55-58 [doi]
• A Neural Network Accelerator With Integrated Feature Extraction Processor for a Freezing of Gait Detection SystemVal Mikos, Chun-Huat Heng, Arthur Tay, Shih-Cheng Yen, Nicole Shuang Yu Chia, Karen Koh Mui Ling, Dawn May Leng Tan, Wing Lok Au. 59-62 [doi]
• A 0.25-27Gb/s Wideband PAM4/NRZ Transceiver with Adaptive Power CDR for 8K SystemYoshihide Komatsu, Akinori Shinmyo, Masami Funabashi, Shuji Kato, Kazuya Hatooka, Kenji Tanaka, Mayuko Fujita, Kouichi Fukuda. 63-66 [doi]
• A Fully-Integrated 25Gb/s Low-Noise TIA+CDR Optical Receiver designed in 40nm-CMOSJuncheng Wang, XueFeng Chen, Shang Hu, Yaxin Cai, Rui Bai, Xin Wang, Yuanxi Zhang, Shenglong Zhuo, Chang Liu, Bozhi Yin, Jianxu Ma, Hao Yan, Jiangao Xuan, Milton Lu, Tao Xia, Nan Qi, Patrick Yin Chiang. 67-68 [doi]
• A Low Input Referred Noise and Low Crosstalk Noise 25 Gb/s Transimpedance Amplifier with Inductor-Less Bandwidth CompensationAkitaka Hiratsuka, Akira Tsuchiya, Kcnji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera. 69-72 [doi]
• 2, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking LoopMin-Seong Choo, Han-Gon Ko, Sung-Yong Cho, KwangHo Lee, Deog Kyoon Jeong. 73-76 [doi]
• A 28.16-Gb/s Area-Efficient 60GHz CMOS Bi-Directional Transceiver for IEEE 802.11ayJian Pang, Korkut Kaan Tokgoz, Shotaro Maki, Zheng Li, Xueting Luo, Ibrahim Abdo, Seitarou Kawai, Hanli Liu, Bangan Liu, Makihiko Katsuragi, Kento Kimura, Atsushi Shirane, Kenichi Okada. 77-78 [doi]
• A 77-GHz Mixed-Mode FMCW Generator Based on a Vernier TDC with Dual Rising-Edge Fractional-Phase DetectorJianxi Wu, Zipeng Chen, Wei Zheng, Yibo Liu, Shufu Wang, Nan Qi, Baoyong Chi. 79-82 [doi]
• A CMOS 76-81 GHz 2TX 3RX FMCW Radar Transceiver Based on Mixed-Mode PLL Chirp GeneratorTaikun Ma, Zipeng Chen, Jianxi Wu, Wei Zheng, Shufu Wang, Nan Qi, Baoyong Chi. 83-86 [doi]
• A 25 fps 32 × 24 Digital CMOS Terahertz Image SensorTong Fang, Runjiang Dou, Liyuan Liu, Jian Liu, Nanjian Wu. 87-90 [doi]
• A 3.9μW, 81.3dB SNDR, DC-coupled, Time-based Neural Recording IC with Degeneration R-DAC for Bidirectional Neural Interface in 180nm CMOSHyuntak Jeon, Jun-Suk Bang, Yoontae Jung, Taeju Lee, Yeseul Jeon, Seok-Tae Koh, Jaesuk Choi, Doojin Jang, Soonyoung Hong, Minkyu Je. 91-92 [doi]
• A Second-Order Purely VCO-Based CT Δ∑ ADC Using a Modified DPLL in 40-nm CMOSYi Zhong, Shaolan Li, Arindam Sanyal, Xiyuan Tang, Linxiao Shen, Siliang Wu, Nan Sun. 93-94 [doi]
• A 1-V 3.1-ppm/°C 0.8-μW Bandgap Reference with Piecewise Exponential Curvature CompensationHongrui Luo, Quan Sun, Ruizhi Zhang, Hong Zhang. 97-98 [doi]
• A 40nW, Sub-IV Truly 'Digital' Reverse Bandgap Reference Using Bulk-Diodes in 16nm FinFETMatthias Eberlein, Georgios Panagopoulos, Harald Pretl. 99-102 [doi]
• A 0.6V 1.63fJ/c.-s. Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-Capacitor TDDI SystemYao-Sheng Hu, Li-Yu Huang, Hsin-Shu Chen. 103-106 [doi]
• Design of a 2.45-GHz RF Energy Harvester for SWIPT IoT smart sensorsPengcheng Xu, Denis Flandre, David Bol. 107-110 [doi]
• A 6.78-200 MHz Offset-Compensated Active Rectifier with Dynamic Logic Comparator for mm-size Wirelessly Powered ImplantsJianming Zhao, Yuan Gao. 111-114 [doi]
• Photovoltaic-Assisted Self-Vth-Cancellation CMOS RF Rectifier for Wide Power Range OperationRen Usami, Takao Komiyama, Yasunori Chonan, Hiroyuki Yamaguchi, Koji Kotani. 115-118 [doi]
• Stable, Self-Biased and High-Gain Organic Amplifiers with Reduced Parameter Variation EffectMasoud Seifaei, Daniel DeDorigo, David Ingvar Fleig, Matthias Kuhl, Ute Zschieschang, Hagen Klauk, Yiannos Manoli. 119-122 [doi]
• An Encryption-Authentication Unified A/D Conversion Scheme for IoT Sensor NodesVinod V. Gadde, Hiromitsu Awano, Makoto Ikeda. 123-126 [doi]
• A 28mn 320Kb TCAM Macro with Sub-0.8ns Search Time and 3.5+x Improvement in Delay-Area-Energy Product using Split-Controlled Single-Load 14T CellCheng-Xin Xue, Wei-Cheng Zhao, Tzu-Hsien Yang, Yi-Ju Chen, Hiroyuki Yamauchi, Meng-Fan Chang. 127-128 [doi]
• A 6.8 TOPS/W Energy Efficiency, 1.5µW Power Consumption, Pulse Width Modulation Neuromorphic Circuits for Near-Data Computing with SSDKota Tsurumi, Kenta Suzuki, Ken Takeuchi. 129-132 [doi]
• A 28mn FD-SOI 4KB Radiation-hardened 12T SRAM Macro with 0.6 ~ 1V Wide Dynamic Voltage Scaling for Space ApplicationsTrang Le Dinh Dang, Dongkyu Seo, Jin-Woo Han, Jinsang Kim, Ik Joon Chang. 133-134 [doi]
• 2 and K-means Clustering for Power ReductionKeji Zhou, Xiaoyong Xue, Jianguo Yang, Xiaoxin Xu, Hangbing Lv, Mingyu Wang, Mingre Jing, Wenjun Liu, Xiaoyang Zeng, Steve S. Chung, Jing Li, Ming Liu. 135-138 [doi]
• An Enhanced Built-off-Test Transceiver with Wide-range, Self-calibration Engine for 3.2 Gb/s/pin DDR4 SDRAMJoung-Wook Moon, Hye-Sung Yoo, Hundai Choi, Il-Won Park, Seok-Yong Kang, Jun-Bae Kim, Haeyoung Chung, Kiho Kim, Dong-Hun Lee, Ki-Jae Song, Seok-Hun Hyun, Indal Song, Young-Soo Sohn, Yong-Ho Cho, Jung Hwan Choi, Kwang-Il Park, Seong-Jin Jang. 139-142 [doi]
• 31.3 μs/Signature-Generation 256-bit 픽p ECDSA CryptoprocessorShotaro Sugiyama, Hiromitsu Awano, Makoto Ikeda. 153-156 [doi]
• A Physically Unclonable Function with 0% BER Using Soft Oxide Breakdown in 40nm CMOSKai-Hsin Chuang, Erik Bury, Robin Degraeve, Ben Kaczer, Dimitri Linten, Ingrid Verbauwhede. 157-160 [doi]
• 2 2D Power-Gated EE SRAM Physically Unclonable Function With Dark-Bit Detection TechniqueKunyang Liu, Yue Min, Xuan Yang, Hanfeng Sun, Hirofumi Shinohara. 161-164 [doi]
• An 82.1%-Power-Efficiency Single-Inductor Triple-Source Quad-Mode Energy Harvesting Interface with Automatic Source Selection and Reversely Polarized Energy RecyclingChih-Lun Lo, Hao-Chung Cheng, Pei-Chun Liao, Yi-Lun Chen, Po-Hung Chen. 165-168 [doi]
• A Transient-Enhanced Constant On-Time Buck Converter with Light-Load Efficiency OptimizationMao-Ling Chiu, Tzu-Hsuan Yang, Tsung-Hsien Lin. 169-170 [doi]
• A 99.2% Tracking Accuracy Single-Inductor Quadruple-Input-Quadruple-Output Buck-Boost Converter Topology with Periodical Interval Perturbation and Observation MPPTChao-Jen Huang, Yao-Sheng Ma, Wen-Hau Yang, Yen-Ting Lin, Chun-Chieh Kuo, Ke-Homg Chen, Hsiao-Jung Liu, Pei-Shan Yu, Fang-Chih Chu, Ching-Ju Lin, Hong-Wen Huang, Kuo-Chih Hung, Yuan-Hua Chu, Ying-Hsi Lin, Suhwan Kim, Krishnan Ravichandran. 171-174 [doi]
• A Digital Multiphase Converter with Sensor-less Current and Thermal Balance MechanismKai-Yu Hu, Yu-Sin Chen, Chien-Hung Tsai. 175-178 [doi]
• A Fully-integrated LC-Oscillator Based Buck Regulator with Autonomous Resonant Switching for Low-Power ApplicationsTianyu Jia, Jie Gu. 179-182 [doi]
• A bulk 65nm Cortex-M0+ SoC with All-Digital Forward Body Bias for 4.3X Subthreshold SpeedupPranay Prabhat, Graham Knight, Supreet Jeloka, Sheng Yang, James Myers. 183-186 [doi]
• A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a Time-based Front-end and a Digital EqualizerPo-Wei Chiu, Muqing Liu, Qianying Tang, Chris H. Kim. 187-190 [doi]
• A 2.69 Mbps/mW 1.09 Mbps/kGE Conjugate Gradient-based MMSE Detector for 64-QAM 128×8 Massive MIMO SystemsGuiqiang Peng, Leibo Liu, Qiushi Wei, Yao Wang, Shouyi Yin, Shaojun Wei. 191-194 [doi]
• A Fully Standard-Cell Based On-Chip BTI and HCI Monitor with 6.2x BTI sensitivity and 3.6x HCI sensitivity at 7 nm Fin-FET ProcessMitsuhiko Igarashi, Yuuki Uchida, Yoshio Takazawa, Yasumasa Tsukamoto, Koji Shibutani, Koji Nii. 195-196 [doi]
• A 140 nW, 32.768 kHz, 1.9 ppm/°C Leakage-Based Digitally Relocked Clock Reference with 0.1 ppm Long-Term Stability in 28nm FD-SOIGuenole Lallement, Fady Abouzeid, Thierry Di Gilio, Philippe Roche, Jean-Luc Autran. 197-200 [doi]
• A 2× Blind Oversampling FSE Receiver with Combined Adaptive Equalization and Infinite-Range Timing RecoverySeuk Son, Hwanseok Yeo, Sigang Ryu, Jaeha Kim. 201-204 [doi]
• A Bimodal (NRZ/PAM-4) ISI Tolerant Timing Recovery with Adaptive DDJ EqualizationMasum Hossain, Aurangozeb, Nhat Nguyen. 205-208 [doi]
• A 12-Gb/s AC-Coupled FFE TX With Adaptive Relaxed Impedance Matching Achieving Adaptation Range of 35-75Ω Z0 and 30-550Ω RRXMinsoo Choi, Myungguk Lee, Byungsub Kim. 209-212 [doi]
• A 40 Gb/s PAM-4 Receiver with 2-Tap DFE Based on Automatically Non-Even Level TrackingChia-Tse Hung, Yu-Ping Huang, Wei-Zen Chen. 213-214 [doi]
• A 1.6-GHz 3.3-mW 1.5-MHz Wide Bandwidth ΔΣ Fractional-N PLL with a Single Path FIR Phase Noise FilteringJingcheng Tao, Chun-Huat Heng. 215-218 [doi]
• A 37-GHz-Input Divide-by-36 Injection-Locked Frequency Divider with 1.6-GHz Lock RangeSangyeop Lee, Kyoya Takano, Ruibing Dong, Shuhei Amakawa, Takeshi Yoshida, Minoru Fujishima. 219-222 [doi]
• A 37.5-45. lGHz Superharmonic-Coupled QVCO with Tunable Phase Accuracy in 28nm Bulk CMOSLuya Zhang, Ali Ameri, Yi-An Li, Nai-Chung Kuo, Mekhail Anwar, Ali M. Niknejad. 223-226 [doi]
• A Fast Auto-Frequency Calibration Technique for Wideband PLL with Wide Reference Frequency RangeZhao Zhang, Jincheng Yang, Liyuan Liu, Nan Qi, Peng Feng, Jian Liu, Nanjian Wu. 227-230 [doi]
• A Sub-Picosecond Hybrid DLL for Large-Scale Phased Array SynchronizationMatan Gal-Katziri, Ali Hajimiri. 231-234 [doi]
• A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating SamplerWenning Jiang, Yan Zhu 0001, Chi-Hang Chan, Boris Murmann, Seng-Pan U, Rui Paulo Martins. 235-238 [doi]
• A 15.1-mW 6-GS/s 6-bit Flash ADC with Selectively Activated 8× Time-Domain InterpolationIl-Min Yi, Naoki Miura, Hiroyuki Fukuyama, Hideyuki Nosaka. 239-242 [doi]
• A 38-mW 7-bit 5-GS/s Time-Interleaved SAR ADC with Background Skew CalibrationYung-Hui Chung, Chia Yi Hu, Che-Wei Chang. 243-246 [doi]
• A 0.6-to-1V 10k-to-100kHz BW 11.7b-ENOB Noise-Shaping SAR ADC for IoT sensor applications in 28-nm CMOSYoung Ha Hwang, Yoonho Song, Jun-Eun Park, Deog Kyoon Jeong. 247-248 [doi]
• A Calibration-Free 0.7-V 13-bit 10-MS/s Full-Analog SAR ADC with Continuous-Time Feedforward Cascaded (CTFC) Op-AmpsKwuang-Han Chang, Chih-Cheng Hsieh. 249-252 [doi]
• An 89.55dB-SFDR 179.6dB-FoMs 12-bit lMS/s SAR-Assisted SAR ADC with Weight-Split Compensation CalibrationYao-Sheng Hu, Jhao-Huei Lin, Ding-Guo Lin, Kai-Yue Lin, Hsin-Shu Chen. 253-256 [doi]
• An Image Recognition Processor with Time-domain Accelerators using Efficient Time Encoding and Non-linear Logic OperationZhengyu Chen, Jie Gu. 257-260 [doi]
• A 95pJ/label Wide-Range Depth-Estimation Processor for Full-HD Light-Field Applications on FPGALi-De Chen, Yu-Ta Lu, Yu-Ling Hsiao, Bo-Hsiang Yang, Wei-Chi Chen, Chao-Tsung Huang. 261-262 [doi]
• A 280mV 3.1pJ/code Huffman Decoder for DEFLATE Decompression Featuring Opportunistic Code Skip and 3-way Symbol Generation in 14nm Tri-gate CMOSSudhir Satpathy, Sanu Mathew, Vikram Suresh, Vinodh Gopal, James Guilford, Mark Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy. 263-266 [doi]
• A Wearable Auto-Patient Adaptive ECG Processor for Shockable Cardiac ArrhythmiaSyed Muhammad Abubakar, Muhammad Rizwan Khan, Wala Saadeh, Muhammad Awais Bin Altaf. 267-268 [doi]
• A Capacitance-to-Digital Converter Integrated in a 32bit Microcontroller for 3D Gesture SensingMitsuru Hiraki, Sugako Otani, Masao Ito, Takuya Mizokami, Masahiro Araki, Hiroyuki Kondo. 269-272 [doi]
• A 104.8TOPS/W One-Shot Time-Based Neuromorphic Chip Employing Dynamic Threshold Error Correction in 65nmLuke R. Everson, Muqing Liu, Nakul Pande, Chris H. Kim. 273-276 [doi]
• A 137-μW Area-Efficient Real-Time Gesture Recognition System for Smart Wearable DevicesTaegeun Yoo, Van Loi Le, Ju Eon Kim, Ngoc Le Ba, Kwang-Hyun Baek, Tony. T. Kim. 277-280 [doi]
• A 655Mbps Successive-Cancellation Decoder for a 1024-bit Polar Code in 180nm CMOSHye-Yeon Yoon, Seung-Jun Hwang, Tae-Hwan Kim. 281-284 [doi]
• A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFETStevo Bailey, Jaeduk Han, Paul Rigge, Richard Lin, Eric Chang, Howard Mao, Zhongkai Wang, Chick Markley, Adam M. Izraelevitz, Angie Wang, Nathan Narevsky, Woo-Rham Bae, Steve Shauck, Sergio Montano, Justin Norsworthy, Munir Razzaque, Wen Hau Ma, Akalu Lentiro, Matthew Doerflein, Darin Heckendorn, Jim McGrath, Franco DeSeta, Ronen Shoham, Mike Stellfox, Mark Snowden, Joseph Cole, Dan Fuhrman, Brian C. Richards, Jonathan Bachrach, Elad Alon, Borivoje Nikolic. 285-288 [doi]
• A Compact High Efficiency and High Power Front-end Module for GSM/EDGE/TD-SCDMA/TD-LTE Applications in 0.13um CMOSShihai He, Fengxiong Peng, Linjian Xu, Hao Meng, Yongxue Qian. 289-292 [doi]
• A 2.4-GHz Single-Pin Antenna Interface RF Front-End with a Function-Reuse Single-MOS VCO-PA and a Push-Pull LNAKai Xu, Jun Yin, Pui-In Mak, Robert Bogdan Staszewski, Rui P. Martins. 293-294 [doi]
• A 6-8GHZ 200MHz Bandwidth 9-Channel VWB Transceiver with 8 Frequency-Hopping SubbandsHaixin Song, Dang Liu, Woogeun Rhee, Zhihua Wang. 295-298 [doi]
• A 0.46-2.1 GHz Spurious and Oscillator-Pulling Free LO Generator for Cellular NB-IoT Transmitter with 23 dBm Integrated PAs in 28nm CMOSJaewon Choi, Nam-Seog Kim, Juyoung Han, Thomas Byunghak Cho. 299-302 [doi]
• A 152μW -99dBm BPSK/16-QAM OFDM Receiver for LPWAN ApplicationsAvish Kosari, Milad Moosavifar, David D. Wentzloff. 303-306 [doi]