Yuriy M. Greshishchev - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 16 from 16

2023

Guest Editorial IEEE 2022 BiCMOS and Compound Semiconductor Integrated Circuits and Technology SymposiumYuriy M. Greshishchev. jssc, 58(9):2405-2406, September 2023. [doi]

2019

2011

A 56GS/S 6b DAC in 65nm CMOS with 256×6b memoryYuriy M. Greshishchev, Daniel Pollex, Shing-Chi Wang, Marinette Besson, Philip Flemeke, Stefan Szilagyi, Jorge Aguirre, Chris Falt, Naim Ben Hamida, Robert Gibbins, Peter Schvan. isscc 2011: 194-196 [doi]

2010

2009

Clock recovery for a 40 Gb/s QPSK optical receiverNaim Ben Hamida, John Sitch, Philip Flemke, Daniel Pollex, Peter Schvan, Yuriy M. Greshishchev, Shing-Chi Wang, Chris Falt. icecsys 2009: 695-698 [doi]

2008

2007

Optical CommunicationsSung Min Park, Yuriy M. Greshishchev. isscc 2007: 40-41 [doi]

2005

Introduction to the Special Issue on the 2005 IEEE International Solid-State Circuits ConferenceAxel Thomsen, Jacques Christophe Rudell, Yuriy M. Greshishchev, J. E. D. Hurwitz. jssc, 40(12):2359-2363, 2005. [doi]

2000

A fully integrated SiGe receiver IC for 10-Gb/s data rateYuriy M. Greshishchev, Peter Schvan, Jonathan L. Showell, Mu-Liang Xu, Jugnu J. Ojha, Jonathan E. Rogers. jssc, 35(12):1949-1957, 2000. [doi]

SiGe clock and data recovery IC with linear-type PLL for 10-Gb/s SONET applicationYuriy M. Greshishchev, Peter Schvan. jssc, 35(9):1353-1359, 2000. [doi]

1999

A 60-dB gain, 55-dB dynamic range, 10-Gb/s broad-band SiGe HBT limiting amplifierYuriy M. Greshishchev, Peter Schvan. jssc, 34(12):1914-1920, 1999. [doi]

1997

Phase-correcting feedback system for class E power amplifierTirdad Sowlati, Yuriy M. Greshishchev, C. André T. Salama. jssc, 32(4):544-549, 1997. [doi]

1995

Linear transmitter design using high efficiency Class E power amplifierTirdad Sowlati, Yuriy M. Greshishchev, C. Andre T. Salama, Gord Rabjohn, John Sitch. pimrc 1995: 1233 [doi]

Sign in or sign up to see more results.

runs on WebDSL