Peter Schvan - researchr alias

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Viewing Publication 1 - 19 from 19

2021

200-GS/s ADC Front-End Employing 25% Duty Cycle Quadrature Clock GeneratorNaftali Weiss, Gregory Cooke, Peter Schvan, Pascal Chevalier 0002, Andreia Cathelin, Sorin P. Voinigescu. esscirc 2021: 483-486 [doi]

2020

Data Converter Interleaving: Current Trends and Future PerspectivesChristian Schmidt 0001, Hiroshi Yamazaki, Gregory Raybon, Peter Schvan, Erwan Pincemin, S. J. Ben Yoo, Daniel J. Blumenthal, Takayuki Mizuno, Robert Elschner. cm, 58(5):19-25, 2020. [doi]

2019

Coherent Transceiver for High Speed Optical Communications: Opportunities and ChallengesSebastien Blais, Yuriy M. Greshishchev, Peter Schvan, Ian Betty, Douglas McGhan. bcicts 2019: 1-6 [doi]

Design of a 55-nm SiGe BiCMOS 5-bit Time-Interleaved Flash ADC for 64-Gbd 16-QAM Fiberoptics ApplicationsAlireza Zandieh, Peter Schvan, Sorin P. Voinigescu. jssc, 54(9):2375-2387, 2019. [doi]

2018

A 2x-Oversampling, 128-GS/s 5-bit Flash ADC for 64-GBaud ApplicationsAlireza Zandieh, Peter Schvan, Sorin P. Voinigescu. bcicts 2018: 52-55 [doi]

2016

55-nm SiGe BiCMOS Distributed Amplifier Topologies for Time-Interleaved 120-Gb/s Fiber-Optic Receivers and TransmittersJames Hoffman, Stefan Shopov, Pascal Chevalier, Andreia Cathelin, Peter Schvan, Sorin P. Voinigescu. jssc, 51(9):2040-2053, 2016. [doi]

2011

2010

2009

Clock recovery for a 40 Gb/s QPSK optical receiverNaim Ben Hamida, John Sitch, Philip Flemke, Daniel Pollex, Peter Schvan, Yuriy M. Greshishchev, Shing-Chi Wang, Chris Falt. icecsys 2009: 695-698 [doi]

2008

A 24GS/s 6b ADC in 90nm CMOSPeter Schvan, Jérôme Bach, Chris Falt, Philip Flemke, Robert Gibbins, Yuriy M. Greshishchev, Naim Ben Hamida, Daniel Pollex, John Sitch, Shing-Chi Wang, John Wolczanski. isscc 2008: 544-545 [doi]

2007

Low-Voltage Topologies for 40-Gb/s Circuits in Nanoscale CMOSTheodoros Chalvatzis, Kenneth H. K. Yau, Ricardo Andres Aroca, Peter Schvan, Ming-Ta Yang, Sorin P. Voinigescu. jssc, 42(7):1564-1573, 2007. [doi]

Algorithmic Design of CMOS LNAs and PAs for 60-GHz RadioTerry Yao, Michael Q. Gordon, Keith K. W. Tang, Kenneth H. K. Yau, Ming-Ta Yang, Peter Schvan, Sorin P. Voinigescu. jssc, 42(5):1044-1057, 2007. [doi]

2006

A 22GS/s 5b adc in 0.13µm SiGe BiCMOSPeter Schvan, Daniel Pollex, Shing-Chi Wang, Chris Falt, Naim Ben Hamida. isscc 2006: 2340-2349 [doi]

2000

A fully integrated SiGe receiver IC for 10-Gb/s data rateYuriy M. Greshishchev, Peter Schvan, Jonathan L. Showell, Mu-Liang Xu, Jugnu J. Ojha, Jonathan E. Rogers. jssc, 35(12):1949-1957, 2000. [doi]

SiGe clock and data recovery IC with linear-type PLL for 10-Gb/s SONET applicationYuriy M. Greshishchev, Peter Schvan. jssc, 35(9):1353-1359, 2000. [doi]

1999

A 60-dB gain, 55-dB dynamic range, 10-Gb/s broad-band SiGe HBT limiting amplifierYuriy M. Greshishchev, Peter Schvan. jssc, 34(12):1914-1920, 1999. [doi]

1997

A scalable high-frequency noise model for bipolar transistors with application to optimal transistor sizing for low-noise amplifier designSorin P. Voinigescu, Michael C. Maliepaard, Jonathan L. Showell, Greg E. Babcock, David Marchesan, Michael Schroter, Peter Schvan, David L. Harame. jssc, 32(9):1430-1439, 1997. [doi]

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