Amr Elshazly, Rajesh Inti, Wenjing Yin, Brian Young, Pavan Kumar Hanumolu. A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration. In IEEE International Solid-State Circuits Conference, ISSCC 2011, Digest of Technical Papers, San Francisco, CA, USA, 20-24 February, 2011. pages 92-94, IEEE, 2011. [doi]
Abstract is missing.