Naga Sasidhar - researchr alias

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Viewing Publication 1 - 5 from 5

2012

Rail-to-Rail Input Pipelined ADC Incorporating Multistage Signal MappingNaga Sasidhar, David Gubbins, Pavan Kumar Hanumolu, Un-Ku Moon. tcas, 59-II(9):558-562, 2012. [doi]

2011

A 0.5-to-2.5Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error toleranceRajesh Inti, Wenjing Yin, Amr Elshazly, Naga Sasidhar, Pavan Kumar Hanumolu. isscc 2011: 438-450 [doi]

A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error ToleranceRajesh Inti, Wenjing Yin, Amr Elshazly, Naga Sasidhar, Pavan Kumar Hanumolu. jssc, 46(12):3150-3162, 2011. [doi]

2009

A Low Power Pipelined ADC Using Capacitor and Opamp Sharing Technique With a Scheme to Cancel the Effect of Signal Dependent KickbackNaga Sasidhar, Youn-Jae Kook, Seiji Takeuchi, Koichi Hamashita, Kaoru Takasuka, Pavan Kumar Hanumolu, Un-Ku Moon. jssc, 44(9):2392-2401, 2009. [doi]

2006

A Distortion Compensating Flash Analog-to-Digital Conversion TechniqueVenkata Srinivas, Shanthi Pavan, Ashish Lachhwani, Naga Sasidhar. jssc, 41(9):1959-1969, 2006. [doi]

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