Claudio Nani - researchr alias

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Viewing Publication 1 - 15 from 15

2024

2023

Analysis and Design of a Low Power Double Tail Comparator with Dynamic Bias in 5nm FinFET TechnologyValentina Marazzi, Enrico Monaco, Claudio Nani, Danilo Manstretta. prime 2023: 29-32 [doi]

A 0.94 V Dynamic Bias Double Tail Comparator for High-Speed Applications in 5 nm TechnologyValentina Marazzi, Enrico Monaco, Claudio Nani, Danilo Manstretta. applepies 2024: 68-73 [doi]

2021

Delay-lines jitter modeling and efficiency analysis in FinFET technologyAlessio Di Pasquo, Enrico Monaco, Claudio Nani, Luca Fanucci. icecsys 2021: 1-5 [doi]

A High Linearity Driver with Embedded Interleaved Track-and-Hold Array for High-Speed ADCAlessio Di Pasquo, Claudio Nani, Enrico Monaco, Luca Fanucci. iscas 2021: 1-5 [doi]

2020

A 243-mW 1.25-56-Gb/s Continuous Range PAM-4 42.5-dB IL ADC/DAC-Based Transceiver in 7-nm FinFETMatteo Pisati, Alberto Minuti, Giacomino Bollati, Fabio Giunco, Roberto G. Massolini, Giovanni Cesura, Fernando De Bernardinis, Paolo Pascale, Claudio Nani, Nicola Ghittori, Enrico Pozzati, Marco Sosio, Marco Garampazzi, Antonio Milani. jssc, 55(1):6-18, 2020. [doi]

2019

2016

27.8 A 0.076mm2 12b 26.5mW 600MS/s 4×-interleaved subranging SAR-ΔΣ ADC with on-chip buffer in 28nm CMOSAlessandro Venca, Nicola Ghittori, Alessandro Bosi, Claudio Nani. isscc 2016: 470-472 [doi]

A 0.076 mm2 12 b 26.5 mW 600 MS/s 4-Way Interleaved Subranging SAR-ΔΣ ADC With On-Chip Buffer in 28 nm CMOSAlessandro Venca, Nicola Ghittori, Alessandro Bosi, Claudio Nani. jssc, 51(12):2951-2962, 2016. [doi]

2012

A 6-Bit 50-MS/s Threshold Configuring SAR ADC in 90-nm Digital CMOSPierluigi Nuzzo, Claudio Nani, Costantino Armiento, Alberto L. Sangiovanni-Vincentelli, Jan Craninckx, Geert Van der Plas. tcas, 59-I(1):80-92, 2012. [doi]

2011

A 480mW 2.6GS/s 10b 65nm CMOS time-interleaved ADC with 48.5dB SNDR up to NyquistKonstantinos Doris, Erwin Janssen, Claudio Nani, Athon Zanikopoulos, Gerard Van der Weide. isscc 2011: 180-182 [doi]

A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOSKostas Doris, Erwin Janssen, Claudio Nani, Athon Zanikopoulos, Gerard Van der Weide. jssc, 46(12):2821-2833, 2011. [doi]

2009

Architectural Exploration and Design of Time-Interleaved SAR Arrays for Low-Power and High Speed A/D ConvertersSergio Saponara, Pierluigi Nuzzo, Claudio Nani, Geert Van der Plas, Luca Fanucci. ieicet, 92-C(6):843-851, 2009. [doi]

2008

Mixed-Signal Design Space Exploration of Time-Interleaved A/D Converters for Ultra-Wide Band ApplicationsPierluigi Nuzzo, Claudio Nani, Sergio Saponara, Luca Fanucci, Geert Van der Plas. date 2008: 1390-1393 [doi]

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