Abstract is missing.
- Automatically Realising Embedded Systems from High-Level Functional ModelsPieter J. Mosterman, Don Orofino, Janos Sztipanovits, Ahmed Amine Jerraya, Wido Kruijtzer, Víctor Reyes, Christos G. Cassandras, Grant Martin. [doi]
- From Transistor to PLL - Analogue Design and EDA MethodsDavid Binkley, Helmut E. Graeb, Georges G. E. Gielen, Jaijeet S. Roychowdhury. [doi]
- DfM in the Analogue and Digital WorldCarsten Elgert, Volker Herbig, Anton Ossner, Thomas Harms, Emmanuel Blanc. [doi]
- System-Level Design and Application Mapping for Wireless and Multimedia MPSoC ArchitecturesRainer Leupers, Gerd Ascheid, Wilfried Verachtert, Tom Ashby, Arnout Vandecappelle. [doi]
- Design Flows, Communication Based Design and Architectures in Automotive Electronic SystemsJürgen Becker, Michael Hübner, Robert Esser, Andreas Herkersdorf, Walter Stechele, Vera Lauer. [doi]
- Power Gating for Ultra-low Leakage: Physics, Design, and AnalysisJerry Frenkil, Ken Choi, Kimiyoshi Usami. [doi]
- Design Variability: Challenges and Solutions at Microarchitecture-Architecture LevelDiana Marculescu, Sani R. Nassif. [doi]
- Heterogeneous System-level Specification Using SystemCEugenio Villar, Axel Jantsch, Christoph Grimm, Tim Kogel. [doi]
- Formal Methods in System and MpSoC Performance Analysis and OptimisationRolf Ernst, Marek Jersak, Hans Sarnowski, Marco Bekooij, Samarjit Chakraborty. [doi]
- Soft Errors: System Effects, Protection Techniques and Case StudiesDimitris Gizopoulos, Kaushik Roy, Subhasish Mitra, Pia Sanda. [doi]
- Power-Aware Testing and Test Strategies for Low Power DevicesDimitris Gizopoulos, Kaushik Roy, Patrick Girard, Nicola Nicolici, Xiaoqing Wen. [doi]
- Designing Micro/Nano Systems for a Safer and Healthier TomorrowGiovanni De Micheli. 1 [doi]
- Perspective on Embedded Systems: Challenges, Solutions and Research PrioritiesDominique Vernay. 2 [doi]
- Cycle-approximate Retargetable Performance Estimation at the Transaction LevelYonghyun Hwang, Samar Abdi, Daniel Gajski. 3-8 [doi]
- A Method for the Efficient Development of Timed and Untimed Transaction-Level Models of Systems-on-ChipJérôme Cornet, Florence Maraninchi, Laurent Maillet-Contoz. 9-14 [doi]
- Integrating RTL IPs into TLM Designs Through Automatic Transactor GenerationNicola Bombieri, Nicola Deganello, Franco Fummi. 15-20 [doi]
- Tailored Solutions for Safety-Installations in the Loetschberg Tunnel - A Project with Importance for the Trans-European Rail TrafficWalter Fuß. 21-25 [doi]
- On the Verification of High-Order Constraint Compliance in IC DesignJan B. Freuer, Goran Jerke, Joachim Gerlach, Wolfgang Nebel. 26-31 [doi]
- Industrial IP Integration Flows based on IP-XACT StandardsWido Kruijtzer, Pieter van der Wolf, Erwin A. de Kock, Jan Stuyt, Wolfgang Ecker, Albrecht Mayer, Serge Hustin, Christophe Amerijckx, Serge De Paoli, Emmanuel Vaumorin. 32-37 [doi]
- A Reconfigurable Application Specific Instruction Set Processor for Convolutional and Turbo Decoding in a SDR EnvironmentTimo Vogt, Norbert Wehn. 38-43 [doi]
- Using Reconfigurable Logic to Optimise GPU Memory AccessesBen Cope, Peter Y. K. Cheung, Wayne Luk. 44-49 [doi]
- Cost-and Power Optimized FPGA based System Integration: Methodologies and Integration of a Low-Power Capacity-based Measurement Application on Xilinx FPGAsKatarina Paulsson, Michael Hübner, Jürgen Becker. 50-55 [doi]
- Design flow for embedded FPGAs based on a flexible architecture templateB. Neumann, Thorsten von Sydow, Holger Blume, Tobias G. Noll. 56-61 [doi]
- Optimal High-Resolution Spectral AnalyzerA. Tchegho, Heinz Mattes, Sebastian Sattler. 62-67 [doi]
- A General Method to Evaluate RF BIST Techniques Based on Non-parametric Density EstimationHaralampos-G. D. Stratigopoulos, Jeanne Tongbong, Salvador Mir. 68-73 [doi]
- Diagnostic Analysis of Static Errors in Multi-Step Analog to Digital ConvertersAmir Zjajo, José Pineda de Gyvez. 74-79 [doi]
- Practical Implementation of a Network Analyzer for Analog BIST ApplicationsManuel J. Barragan Asian, Diego Vázquez, Adoración Rueda. 80-85 [doi]
- Quantitative Evaluation in Embedded System Design: Trends in Modeling and Analysis TechniquesJoost-Pieter Katoen. 86-87 [doi]
- Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded ArchitecturesNicolas Coste, Hubert Garavel, Holger Hermanns, Richard Hersemeule, Yvain Thonnart, Meriem Zidouni. 88-89 [doi]
- Quantitative Evaluation in Embedded System Design: Predicting Battery Lifetime in Mobile DevicesLucia Cloth, Boudewijn R. Haverkort. 90-91 [doi]
- A Framework of Stochastic Power Management Using Hidden Markov ModelYing Tan, Qinru Qiu. 92-97 [doi]
- Harvesting Wasted Heat in a Microprocessor Using Thermoelectric Generators: Modeling, Analysis and MeasurementYu Zhou, Somnath Paul, Swarup Bhunia. 98-103 [doi]
- An Efficient Solar Energy Harvester for Wireless Sensor NodesDavide Brunelli, Luca Benini, Clemens Moser, Lothar Thiele. 104-109 [doi]
- Temperature Control of High-Performance Multi-core Platforms Using Convex OptimizationSrinivasan Murali, Almir Mutapcic, David Atienza, Rajesh Gupta, Stephen P. Boyd, Luca Benini, Giovanni De Micheli. 110-115 [doi]
- Parametric Throughput Analysis of Synchronous Data Flow GraphsAmir Hossein Ghamarian, Marc Geilen, Twan Basten, Sander Stuijk. 116-121 [doi]
- Introducing Preemptive Scheduling in Abstract RTOS Models using Result Oriented ModelingGunar Schirner, Rainer Dömer. 122-127 [doi]
- SystemC-based Modelling, Seamless Refinement, and Synthesis of a JPEG 2000 DecoderKim Grüttner, Frank Oppenheimer, Wolfgang Nebel, Fabien Colas-Bigey, Anne-Marie Fouilliart. 128-133 [doi]
- Modeling and Refining Heterogeneous Systems With SystemC-AMS: Application to WSNMichel Vasilevski, François Pêcheux, Nicolas Beilleau, Hassan Aboushady, Karsten Einwich. 134-139 [doi]
- Sizing Rules for Bipolar Analog Circuit DesignTobias Massier, Helmut E. Graeb, Ulf Schlichtmann. 140-145 [doi]
- Efficient circuit-level modelling of ballistic CNT using piecewise non-linear approximation of mobile charge densityTom J. Kazmierski, Dafeng Zhou, Bashir M. Al-Hashimi. 146-151 [doi]
- A New Approach for Combining Yield and Performance in Behavioural Models for Analogue Integrated CircuitsSawal Ali, Reuben Wilcock, Peter Wilson, Andrew Brown. 152-157 [doi]
- Symbolic Reliability Analysis and Optimization of ECU NetworksMichael Glaß, Martin Lukasiewycz, Felix Reimann, Christian Haubelt, Jürgen Teich. 158-163 [doi]
- Verification of Temporal Properties in Automotive Embedded SoftwareDjones Lettnin, Pradeep Kumar Nalla, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel, Tobias Kirsten, Volker Schonknecht, Stephan Reitemeyer. 164-169 [doi]
- A Novel Approach for EMI Design of Power ElectronicsBernd Stube, Bernd Schröder, Eckart Hoene, Andre Lissner. 170-175 [doi]
- Hardware/software architecture of an algorithm for vision-based real-time vehicle detection in dark environmentsNicolas Alt, Christopher Claus, Walter Stechele. 176-181 [doi]
- Analysis of The Test Data Volume Reduction Benefit of Modular SOC TestingOzgur Sinanoglu, Erik Jan Marinissen. 182-187 [doi]
- Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test PatternsAnders Larsson, Erik Larsson, Krishnendu Chakrabarty, Petru Eles, Zebo Peng. 188-193 [doi]
- An novel Methodology for Reducing SoC Test Data Volume on FPGA-based TestersPaolo Bernardi, Matteo Sonza Reorda. 194-199 [doi]
- Performance Analysis of SoC Architectures Based on Latency-Rate ServersJelte Peter Vink, Kees van Berkel, Pieter van der Wolf. 200-205 [doi]
- Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCsSujan Pandey, Rolf Drechsler. 206-211 [doi]
- Run-time Spatial Mapping of Streaming Applications to a Heterogeneous Multi-Processor System-on-Chip (MPSOC)Philip K. F. Hölzenspies, Johann Hurink, Jan Kuper, Gerard J. M. Smit. 212-217 [doi]
- Architecture Exploration of NAND Flash-based Multimedia CardSungchan Kim, Chanik Park, Soonhoi Ha. 218-223 [doi]
- Resilient Dynamic Power Management under UncertaintyHwisung Jung, Massoud Pedram. 224-229 [doi]
- Robust and Low Complexity Rate Control for Solar Powered SensorsClemens Moser, Lothar Thiele, Davide Brunelli, Luca Benini. 230-235 [doi]
- Energy Aware Dynamic Voltage and Frequency Selection for Real-Time Systems with Energy HarvestingShaobo Liu, Qinru Qiu, Qing Wu. 236-241 [doi]
- Dynamic Voltage Scaling of Supply and Body Bias Exploiting Software Runtime DistributionSungpack Hong, Sungjoo Yoo, Byeong Bin, Kyu-Myung Choi, Soo-Kwan Eo, Taehwan Kim. 242-247 [doi]
- Built-in Clock Skew System for On-line Debug and RepairAtanu Chattopadhyay, Zeljko Zilic. 248-251 [doi]
- Analysis and Optimization of the Recessed Probe Launch for High Frequency Measurements of PCB InterconnectsRenato Rimolo-Donadio, Christian Schuster, Xiaoxiong Gu, Young Hoon Kwark, Mark B. Ritter. 252-255 [doi]
- On Automated Trigger Event Generation in Post-Silicon ValidationHo Fai Ko, Nicola Nicolici. 256-259 [doi]
- Dynamic Round-Robin Task Scheduling to Reduce Cache Misses for Embedded SystemsKen W. Batcher, Robert A. Walker. 260-263 [doi]
- Improving the Efficiency of Run Time Reconfigurable Devices by Configuration LockingYang Qu, Juha-Pekka Soininen, Jari Nurmi. 264-267 [doi]
- Logic Synthesis with Nanowire Crossbar: Reality Check and Standard Cell-based IntegrationMian Dong, Lin Zhong. 268-271 [doi]
- Merged Computation for Whirlpool HashingRicardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis. 272-275 [doi]
- Source-Level Timing Annotation and Simulation for a Heterogeneous MultiprocessorTrevor Meyerowitz, Alberto L. Sangiovanni-Vincentelli, Mirko Sauermann, Dominik Langen. 276-279 [doi]
- Safe Automatic Flight Back and Landing of Aircraft Flight Reconfiguration Function (FRF)Juan Alberto Herreria Garcia. 280-283 [doi]
- PWM-Based Test Stimuli Generation for BIST of High Resolution ADCsDaniela De Venuto, Leonardo Reyneri. 284-287 [doi]
- Temperature-Aware Scheduling and Assignment for Hard Real-Time Applications on MPSoCsThidapat Chantem, Robert P. Dick, Xiaobo Sharon Hu. 288-293 [doi]
- A Formal Approach To The Protocol Converter ProblemKarin Avnit, Vijay D Silva, Arcot Sowmya, S. Ramesh, Sri Parameswaran. 294-299 [doi]
- Cache Aware Mapping of Streaming Applications on a Multiprocessor System-on-ChipArno Moonen, Marco Bekooij, Rene van den Berg, Jef L. van Meerbergen. 300-305 [doi]
- Synthesizing Synchronous Elastic Flow NetworksGreg Hoover, Forrest Brewer. 306-311 [doi]
- Periodic Steady-State Analysis Augmented with Design Equality ConstraintsIgor Vytyaz, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram. 312-317 [doi]
- Analysis of Oscillator Injection Locking by Harmonic Balance MethodMark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Brian J. Mulvaney, Kiran K. Gullapalli. 318-323 [doi]
- Model Checking of Analog Systems using an Analog Specification LanguageSebastian Steinhorst, Lars Hedrich. 324-329 [doi]
- Mapping Semantics of CORBA IDL and GIOP to Open Core Protocol for Portability and Interoperability of SDR Waveform ComponentsGrégory Gailliard, Hugues Balp, Michel Sarlotte, François Verdier. 330-335 [doi]
- On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applicationsLuca Sterpone, M. A. Aguirre, Jonathan Noel Tombs, H. Guzman-Miranda. 336-341 [doi]
- Hot Wire Anemometric MEMS Sensor for Water Flow MonitoringMassimiliano Melani, Lorenzo Bertini, Marco De Marinis, Peter Lange, Francesco D Ascoli, Luca Fanucci. 342-347 [doi]
- Guiding Circuit Level Fault-Tolerance Design with Statistical MethodsDrew C. Ness, David J. Lilja. 348-353 [doi]
- A Delay-efficient Radiation-hard Digital Design Approach Using CWSP ElementsCharu Nagpal, Rajesh Garg, Sunil P. Khatri. 354-359 [doi]
- Towards fault tolerant parallel prefix adders in nanoelectronic systemsWenjing Rao, Alex Orailoglu. 360-365 [doi]
- A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive ClockingSwaroop Ghosh, Patrick Ndai, Kaushik Roy. 366-371 [doi]
- Embedded Tutorial - Software for Wireless Networked Embedded SystemsJan Beutel, M. Beigl, Adam Dunkels, Koen Langendoen. 372 [doi]
- Fine-Grained Supply Gating Through Hypergraph Partitioning and Shannon Decomposition for Active Power ReductionLawrence Leinweber, Swarup Bhunia. 373-378 [doi]
- A Scalable Algorithmic Framework for Row-Based Power-GatingAshoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino. 379-384 [doi]
- Coarse-Grain MTCMOS Sleep Transistor Sizing Using Delay BudgetingEhsan Pakbaznia, Massoud Pedram. 385-390 [doi]
- Physical Architectures of Automotive SystemsT. Forest, Alberto Ferrari, G. Audisio, M. Sabatini, Alberto L. Sangiovanni-Vincentelli, Marco Di Natale. 391-395 [doi]
- A Mutation Model for the SystemC TLM 2.0 Communication InterfacesNicola Bombieri, Franco Fummi, Graziano Pravadelli. 396-401 [doi]
- Efficient Design Validation Based on Cultural AlgorithmsWeixin Wu, Michael S. Hsiao. 402-407 [doi]
- Algorithms for Maximum Satisfiability using Unsatisfiable CoresJoão Marques-Silva, Jordi Planes. 408-413 [doi]
- In-band Cross-Trigger Event Transmission for Transaction-Based DebugShan Tang, Qiang Xu. 414-419 [doi]
- Efficient Representation and Analysis of Power GridsJoão M. S. Silva, Joel R. Phillips, Luis Miguel Silveira. 420-425 [doi]
- High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting SubstrateNavin Srivastava, Roberto Suaya, Kaustav Banerjee. 426-431 [doi]
- ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network AnalysisDuo Li, Sheldon X.-D. Tan, Bruce McGaughy. 432-437 [doi]
- Bandwidth-Centric Optimisation for Area-Constrained Links with Crosstalk Avoidance MethodsBasel Halak, Alexandre Yakovlev. 438-443 [doi]
- Optimizing Near-ML MIMO Detector for SDR Baseband on Parallel Programmable ArchitecturesMin Li, Bruno Bougard, Weiyu Xu, David Novo, Liesbet Van der Perre, Francky Catthoor. 444-449 [doi]
- Vectorization of Reed Solomon Decoding and Mapping on the EVPAkash Kumar, Kees van Berkel. 450-455 [doi]
- A Case Study in Reliability-Aware Design: A Resilient LDPC Code DecoderMatthias May, Matthias Alles, Norbert Wehn. 456-461 [doi]
- Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume ReductionAnshuman Chandra, Felix Ng, Rohit Kapur. 462-467 [doi]
- Scan Chain Organization for Embedded DiagnosisMelanie Elm, Hans-Joachim Wunderlich. 468-473 [doi]
- State Skip LFSRs: Bridging the Gap between Test Data Compression and Test Set Embedding for IP CoresV. Tenentes, Xrysovalantis Kavousianos, Emmanouil Kalligeros. 474-479 [doi]
- Automated Testability Enhancements for Logic Brick LibrariesJason G. Brown, Brian Taylor, Ronald D. Blanton, Larry T. Pileggi. 480-485 [doi]
- A Game-Theoretic Approach to Real-Time System TestingAlexandre David, Kim Guldstrand Larsen, Shuhao Li, Brian Nielsen. 486-491 [doi]
- Modeling Event Stream Hierarchies with Hierarchical Event ModelsJonas Rox, Rolf Ernst. 492-497 [doi]
- Semantics for Model-Based Validation of Continuous/Discrete SystemsLuiza Gheorghe, Faouzi Bouchhima, Gabriela Nicolescu, Hanifa Boucheneb. 498-503 [doi]
- Using UML as Front-end for Heterogeneous Software Code Generation StrategiesLisane B. de Brisolara, Marcio F. da S. Oliveira, Ricardo Miotto Redin, Luís C. Lamb, Luigi Carro, Flávio Rech Wagner. 504-509 [doi]
- Panel Session - Caution Ahead: The Road to Design and Manufacturing at 32 and 22 nmS. Turnoy, Peter Wintermayr, Robert C. Aitken, Rudy Lauwereins, J. Tracy Weed, V. Kiefer, J. Hartmann. 510 [doi]
- Fault Clustering in deep-submicron CMOS ProcessesJan Schat. 511-514 [doi]
- Energy Efficient and High Speed On-Chip Ternary BusChunjie Duan, Sunil P. Khatri. 515-518 [doi]
- Task Scheduling with Configuration Prefetching and Anti-Fragmentation techniques on Dynamically Reconfigurable SystemsFrancesco Redaelli, Marco D. Santambrogio, Donatella Sciuto. 519-522 [doi]
- Fast Analog Circuit Synthesis Using Sensitivity Based Near Neighbor SearchesAlmitra Pradhan, Ranga Vemuri. 523-526 [doi]
- Spatial Correlation Extraction via Random Field Simulation and Production Chip Performance RegressionBao Liu. 527-532 [doi]
- A methodology for improving software design lifecycle in embedded control systemsMohamed El Mongi Ben Gaid, Rémy Kocik, Yves Sorel, Rédha Hamouche. 533-536 [doi]
- Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power NetworkWanping Zhang, Yi Zhu, Wenjian Yu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Nuriyoki Ito, Chung-Kuan Cheng. 537-540 [doi]
- A System Architecture for Reconfigurable Trusted PlatformsBenjamin Glas, Alexander Klimm, Oliver Sander, Klaus D. Müller-Glaser, Jürgen Becker. 541-544 [doi]
- Automatic Generation of Complex Properties for Hardware DesignsFrank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke. 545-548 [doi]
- Software Components for Reliable Automotive SystemsHarald Heinecke, Werner Damm, Bernhard Josko, Alexander Metzner, Hermann Kopetz, Alberto L. Sangiovanni-Vincentelli, Marco Di Natale. 549-554 [doi]
- Model-Based-Design Is Nice But..Herbert Hanselmann. 555 [doi]
- A Simulation Methodology for Worst-Case Response Time Estimation of Distributed Real-Time SystemsSoheil Samii, Sergiu Rafiliu, Petru Eles, Zebo Peng. 556-561 [doi]
- Signal Probability Based Statistical Timing AnalysisBao Liu. 562-567 [doi]
- A Current Source Model for CMOS Logic Cells Considering Multiple Input Switching and Stack EffectBehnam Amelifard, Safar Hatami, Hanif Fatemi, Massoud Pedram. 568-573 [doi]
- Current source based standard cell model for accurate signal integrity and timing analysisAmit Goel, Sarma B. K. Vrudhula. 574-579 [doi]
- An Efficient Method for Chip-Level Statistical Capacitance Extraction Considering Process Variations with Spatial CorrelationWangyang Zhang, Wenjian Yu, Zeyi Wang, Zhiping Yu, Rong Jiang, Jinjun Xiong. 580-585 [doi]
- SPARE - a Scalable algorithm for passive, structure preserving, Parameter-Aware model order REductionJorge Fernandez Villena, Luis Miguel Silveira. 586-591 [doi]
- Transistor-Specific Delay Modeling for SSTABrian Cline, Kaviraj Chopra, David Blaauw, Andres Torres, Savithri Sundareswaran. 592-597 [doi]
- Generic Multi-Phase Software-Pipelined Partial-FFT on Instruction-Level-Parallel Architectures and SDR Baseband ApplicationsMin Li, David Novo, Bruno Bougard, Liesbet Van der Perre, Francky Catthoor. 598-603 [doi]
- A Novel Recursive Algorithm for Bit-Efficient Realization of Arbitrary Length Inverse Modified Cosine TransformsRalf König, Timo Stripf, Jürgen Becker. 604-609 [doi]
- Definition and SIMD Implementation of a Multi-Processing Architecture Approach on FPGAPhilippe Bonnot, Fabrice Lemonnier, Gilbert Edelin, Gerard Gaillat, Olivier Ruch, Pascal Gauget. 610-615 [doi]
- On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS CircuitsAswin Sreedhar, Alodeep Sanyal, Sandip Kundu. 616-621 [doi]
- Optimal Margin Computation for At-Speed TestJinjun Xiong, Vladimir Zolotov, Chandu Visweswariah, Peter A. Habitz. 622-627 [doi]
- Resistive Bridging Fault Simulation of Industrial CircuitsPiet Engelke, Ilia Polian, Jürgen Schlöffel, Bernd Becker. 628-633 [doi]
- Physically-Aware N-Detect Test Pattern SelectionYen-Tzu Lin, Osei Poku, Naresh K. Bhatti, Ronald D. Blanton. 634-639 [doi]
- Computation of Buffer Capacities for Throughput Constrained and Data Dependent Inter-Task CommunicationMaarten Wiggers, Marco Bekooij, Gerard J. M. Smit. 640-645 [doi]
- Constraint Refinement for Online Verifiable Cross-Layer System AdaptationMinyoung Kim, Mark-Oliver Stehr, Carolyn L. Talcott, Nikil Dutt, Nalini Venkatasubramanian. 646-651 [doi]
- Adaptive Scheduling and Voltage Scaling for Multiprocessor Real-time Applications with Non-deterministic WorkloadParth Malani, Prakash Mukre, Qinru Qiu, Qing Wu. 652-657 [doi]
- Embedded Tutorial - ARTEMIS and ENIAC Joint Undertakings: A New Approach to Conduct Research in EuropeE. Schutz, K. Glinos, D. Beenaert, L. Gide. 658 [doi]
- Methods, Tools and Standards for the Analysis, Evaluation and Design of Modern Automotive ArchitecturesE. Frank, Reinhard Wilhelm, Rolf Ernst, Alberto L. Sangiovanni-Vincentelli, Marco Di Natale. 659-663 [doi]
- Random Stimulus Generation using Entropy and XOR ConstraintsStephen Plaza, Igor L. Markov, Valeria Bertacco. 664-669 [doi]
- MCjammer: Adaptive Verification for Multi-core DesignsIlya Wagner, Valeria Bertacco. 670-675 [doi]
- Efficient Implementation of Native Software Simulation for MPSoCPatrice Gerin, Xavier Guerin, Frédéric Pétrot. 676-681 [doi]
- Simulation-Directed Invariant Mining for Software VerificationXueqi Cheng, Michael S. Hsiao. 682-687 [doi]
- Comparison of Opamp-Based and Comparator-Based Delta-Sigma ModulationMassoud Momeni, Petru Bogdan Bacinschi, Manfred Glesner. 688-693 [doi]
- A Novel Technique for Improving Temperature Independency of Ring-ADCShun Li, Hua Chen, Feng Zhou. 694-697 [doi]
- An Analog On-Chip Adaptive Body Bias Calibration for Reducing Mismatches in Transistor PairsPetru Bogdan Bacinschi, Tudor Murgan, Klaus Koch, Manfred Glesner. 698-703 [doi]
- Integrated approach to energy harvester mixed technology modelling and performance optimisationLeran Wang, Tom J. Kazmierski, Bashir M. Al-Hashimi, Stephen P. Beeby, Russel N. Torah. 704-709 [doi]
- A scalable low-power digital communication network architecture and an automated design path for controlling the analog/RF part of SDR transceiversWolfgang Eberle, Michaël Goffioul. 710-715 [doi]
- A Coarse-Grained Array based Baseband Processor for 100Mbps+ Software Defined RadioBruno Bougard, Bjorn De Sutter, Sebastien Rabou, David Novo, Osman Allam, Steven Dupont, Liesbet Van der Perre. 716-721 [doi]
- Scenario-Based Fixed-point Data Format Refinement to Enable Energy-scalable Software Defined RadiosDavid Novo, Bruno Bougard, Andy Lambrechts, Liesbet Van der Perre, Francky Catthoor. 722-727 [doi]
- Test Strategies for Low Power DevicesC. P. Ravikumar, M. Hirech, X. Wen. 728-733 [doi]
- Thermal Balancing Policy for Streaming Computing on Multiprocessor ArchitecturesFabrizio Mulas, Michele Pittau, Marco Buttu, Salvatore Carta, Andrea Acquaviva, Luca Benini, David Atienza, Giovanni De Micheli. 734-739 [doi]
- A Practical Approach for Reconciling High and Predictable Performance in Non-Regular Parallel ProgramsOlivier Certner, Zheng Li, Pierre Palatin, Olivier Temam, Frederic Arzel, Nathalie Drach. 740-745 [doi]
- Exact and Approximate Task Assignment Algorithms for Pipelined Software SynthesisMatin Hashemi, Soheil Ghiasi. 746-751 [doi]
- Run-time System for an Extensible Embedded Processor with Dynamic Instruction SetLars Bauer, Muhammad Shafique, Stephanie Kreutz, Jörg Henkel. 752-757 [doi]
- Harnessing Horizontal Parallelism and Vertical Instruction Packing of Programs to Improve System Overall EfficiencyHai Lin, Yunsi Fei. 758-763 [doi]
- Instruction Set Extension Exploration in Multiple-Issue ArchitectureI-Wei Wu, Zhi-Yuan Chen, Jean Jyh-Jiun Shann, Chung-Ping Chung. 764-769 [doi]
- Instruction Re-encoding Facilitating Dense Embedded CodeTalal Bonny, Jörg Henkel. 770-775 [doi]
- Test Instrumentation for a Laser Scanning Localization Technique for Analysis of High Speed DRAM devicesMartin Versen, Achim Schramm, Jan Schnepp, Dorina Diaconescu. 776-779 [doi]
- A Mapping Framework for Guided Design Space Exploration of Heterogeneous MP-SoCsBastian Ristau, Torsten Limberg, Gerhard Fettweis. 780-783 [doi]
- Impact of Leakage Current on Data Retention of RF-powered Devices During Amplitude-Modulation-based CommunicationJosef Haid, Bernd Zimek, Thomas Leutgeb, Thomas Kunemund. 784-787 [doi]
- Accuracy-Adaptive Simulation of Transaction Level ModelsMartin Radetzki, Rauf Salimi Khaligh. 788-791 [doi]
- Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-ProcessorJun Wang, Hongbo Zeng, Kun Huang, Ge Zhang, Yan Tang. 792-795 [doi]
- Wire Sizing Alternative - An Uniform Dual-rail Routing ArchitectureFu-Wei Chen, Yi-Yu Liu. 796-799 [doi]
- Structural Synthesis of Four-Quadrant Multiplier Based on Hierarchical TopologyXiaoying Wang, Lars Hedrich. 800-803 [doi]
- A Virtual Prototype for Bluetooth over Ultra Wide Band System Level DesignAlexandre Lewicki, Javier del Prado Pavon, Jacky Talayssat, Eric Dekneuvel, Gilles Jacquemod. 804-807 [doi]
- Re-Examining the Use of Network-on-Chip as Test Access MechanismFeng Yuan, Lin Huang, Qiang Xu. 808-811 [doi]
- Panel Session - The Future Car: Technology, Methods and ToolsAlberto L. Sangiovanni-Vincentelli, Marco Di Natale, Scuola S. Anna, H. Hanselmann, Harald Heinecke, Amar Bouali, Hermann Kopetz, H. Fennel, Thomas Weber. 812 [doi]
- Improving Constant-Coefficient Multiplier Verification by Partial Product IdentificationChao-Yue Lai, Chung-Yang Huang, Kei-Yong Khoo. 813-818 [doi]
- Improved Visibility in One-to-Many Trace ConcretizationKuntal Nanshi, Fabio Somenzi. 819-824 [doi]
- Efficient Symbolic Simulation of Low Level SoftwareTamarah Arons, Elad Elster, Shlomit Ozer, Jonathan Shalev, Eli Singerman. 825-830 [doi]
- Completeness in SMT-based BMC for Software ProgramsMalay K. Ganai, Aarti Gupta. 831-836 [doi]
- Novel Pin Assignment Algorithms for Components with Very High Pin CountsTilo Meister, Jens Lienig, Gisbert Thomke. 837-842 [doi]
- A Generic Standard Cell Design Methodology for Differential Circuit StylesStéphane Badel, Erdem Guleyupoglu, Ozgur Inac, Anna Pena Martinez, Paolo Vietti, Frank K. Gürkaynak, Yusuf Leblebici. 843-848 [doi]
- Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon DevicesAshutosh Chakraborty, Sean X. Shi, David Z. Pan. 849-855 [doi]
- Exploiting Correlation Kernels for Efficient Handling of Intra-Die Spatial Correlation, with Application to Statistical TimingAmith Singhee, Sonia Singhal, Rob A. Rutenbar. 856-861 [doi]
- A Triple-Mode Reconfigurable Sigma-Delta Modulator for Multi-Standard Wireless ApplicationsAlonso Morgado, Rocio del Río, José Manuel de la Rosa. 862-867 [doi]
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- Optimization of Design Flows for Multi-Core x86 Microprocessors in 45 and 32nm Technologies under Productivity ConsiderationsHans-Jürgen Brand. 938-939 [doi]
- Implications of Technology Trends on System DependabilityJacob A. Abraham. 940 [doi]
- Globally Optimized Robust Systems to Overcome Scaled CMOS Reliability ChallengesSubhasish Mitra. 941-946 [doi]
- Software Protection Mechanisms for Dependable SystemsUte Wappler, Martin Muller. 947-952 [doi]
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- System Performance Optimization Methodology for Infineon s 32-Bit Automotive Microcontroller ArchitectureAlbrecht Mayer, Frank Hellwig. 962-966 [doi]
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- Clock Distribution Scheme using Coplanar Transmission LinesVictor H. Cordero, Sunil P. Khatri. 985-990 [doi]
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- Comparison of memory write policies for NoC based Multicore Cache Coherent SystemsPierre Guironnet de Massas, Frédéric Pétrot. 997-1002 [doi]
- Serialized Asynchronous Links for NoCSimon Ogg, Enrico Valli, Bashir M. Al-Hashimi, Alexandre Yakovlev, Crescenzo D Alessandro, Luca Benini. 1003-1008 [doi]
- Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic CircuitsJie Zhang, Nishant Patil, Subhasish Mitra. 1009-1014 [doi]
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- Improvements in Polynomial-Time Feasibility Testing for EDFAlejandro Masrur, Sebastian Drossler, Georg Farber. 1033-1038 [doi]
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- An application-based EDF scheduler for OSEK/VDXClaas Diederichs, Ulrich Margull, Frank Slomka, Gerhard Wirrer. 1045-1050 [doi]
- Time Properties of the BuST Protocol under the NPA Budget Allocation SchemeGianluca Franchino, Giorgio C. Buttazzo, Tullio Facchinetti. 1051-1056 [doi]
- Simultaneous FU and Register Binding Based on Network Flow MethodJason Cong, Junjuan Xu. 1057-1062 [doi]
- A Variation Aware High Level Synthesis FrameworkFeng Wang 0004, Guangyu Sun, Yuan Xie. 1063-1068 [doi]
- EPIC: Ending Piracy of Integrated CircuitsJarrod A. Roy, Farinaz Koushanfar, Igor L. Markov. 1069-1074 [doi]
- VLSI implementation of SISO arithmetic decoders for joint source channel codingSimone Zezza, Guido Masera. 1075-1078 [doi]
- Error Detection/Correction in DNA Algorithmic Self-AssemblyStephen Frechette, Fabrizio Lombardi. 1079-1082 [doi]
- Temperature-Aware Voltage Selection for Energy OptimizationMin Bao, Alexandru Andrei, Petru Eles, Zebo Peng. 1083-1086 [doi]
- A Fast Approximation Algorithm for MIN-ONE SATLei Fang, Michael S. Hsiao. 1087-1090 [doi]
- Deep Submicron Interconnect Timing Model with Quadratic Random Variable AnalysisJun-Kuei Zeng, Chung-Ping Chen. 1091-1094 [doi]
- An efficient algorithm for free resources management on the FPGAYi Lu 0004, Thomas Marconi, Georgi Gaydadjiev, Koen Bertels. 1095-1098 [doi]
- Performance-Constrained Different Cell Count Minimization for Continuously-Sized CircuitsHiroaki Yoshida, Masahiro Fujita. 1099-1102 [doi]
- Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCsSudarshan Bahukudumbi, Krishnendu Chakrabarty, Richard Kacprowicz. 1103-1106 [doi]
- CARbridge, Reduction of System Complexity by Standardisation of the System-Basis-Chips for Automotive ApplicationsPatrick Scheer, Ernst Schmidt, Stefan Burges. 1107-1110 [doi]
- Specification and Design Considerations for Reliable Embedded SystemsAdeel Israr, Sorin A. Huss. 1111-1116 [doi]
- Synthesis of Fault-Tolerant Embedded SystemsPetru Eles, Viacheslav Izosimov, Paul Pop, Zebo Peng. 1117-1122 [doi]
- Reliable Services in an Imperfect WorldHermann Kopetz. 1123 [doi]
- Video Processing Requirements on SoC InfrastructuresPieter van der Wolf, Tomas Henriksson. 1124-1125 [doi]
- Memory Technology for Extended Large-Scale Integration in Future Electronics ApplicationsDinesh Pamunuwa. 1126-1127 [doi]
- Memory-aware NoC Exploration and DesignNikil Dutt. 1128-1129 [doi]
- Incremental Criticality and Yield GradientsJinjun Xiong, Vladimir Zolotov, Chandu Visweswariah. 1130-1135 [doi]
- Latch Modeling for Statistical Timing AnalysisSean X. Shi, Anand Ramalingam, Daifeng Wang, David Z. Pan. 1136-1141 [doi]
- Conditional Partial Order Graphs and Dynamically Reconfigurable Control SynthesisAndrey Mokhov, Alexandre Yakovlev. 1142-1147 [doi]
- Efficient Software Architecture for IPSec Acceleration Using a Programmable Security ProcessorJanar Thoguluva, Anand Raghunathan, Srimat T. Chakradhar. 1148-1153 [doi]
- Operating System Controlled Processor-Memory Bus EncryptionXi Chen, Robert P. Dick, Alok N. Choudhary. 1154-1159 [doi]
- An Efficient FPGA Implementation of Principle Component Analysis based Network Intrusion Detection SystemAbhishek Das, Sanchit Misra, Sumeet Joshi, Joseph Zambreno, Gokhan Memik, Alok N. Choudhary. 1160-1165 [doi]
- A Bridging Fault Model Where Undetectable Faults Imply Logic RedundancyIrith Pomeranz, Sudhakar M. Reddy. 1166-1171 [doi]
- Layout-Aware, IR-Drop Tolerant Transition Fault Pattern GenerationJeremy Lee, Sumit Narayan, Mike Kapralos, Mohammad Tehranipoor. 1172-1177 [doi]
- Multi-Vector Tests: A Path to Perfect Error-Rate TestingShideh Shahidi, Sandeep Gupta. 1178-1183 [doi]
- iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based TestingJia Li, Qiang Xu, Yu Hu, Xiaowei Li. 1184-1189 [doi]
- Hiding Cache Miss Penalty Using Priority-based Execution for Embedded ProcessorsSanghyun Park, Aviral Shrivastava, Yunheung Paek. 1190-1195 [doi]
- Instruction Cache Energy Saving Through Compiler Way-PlacementTimothy M. Jones, Sandro Bartolini, Bruno De Bus, John Cavazos, Michael F. P. O Boyle. 1196-1201 [doi]
- Effective Loop Partitioning and Scheduling under Memory and Register Dual ConstraintsChun Jason Xue, Edwin Hsing-Mean Sha, Zili Shao, Meikang Qiu. 1202-1207 [doi]
- Transparent Reconfigurable Acceleration for Heterogeneous Embedded ApplicationsAntonio Carlos Schneider Beck, Mateus B. Rutzig, Georgi Gaydadjiev, Luigi Carro. 1208-1213 [doi]
- Automatic Selection of Application-Specific Reconfigurable Processor ExtensionsChristophe Wolinski, Krzysztof Kuchcinski. 1214-1219 [doi]
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- Dependability for high-tech systems: an industry-as-laboratory approachEd Brinksma, Jozef Hooman. 1226-1231 [doi]
- User-Aware Dynamic Task Allocation in Networks-on-ChipChen-Ling Chou, Radu Marculescu. 1232-1237 [doi]
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- Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit DesignAjay K. Verma, Philip Brisk, Paolo Ienne. 1250-1255 [doi]
- Improving Synthesis of Compressor Trees on FPGAs via Integer Linear ProgrammingHadi Parandeh-Afshar, Philip Brisk, Paolo Ienne. 1256-1261 [doi]
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- Comparison of Boolean Satisfiability Encodings on FPGA Detailed Routing ProblemsMiroslav N. Velev, Ping Gao 0002. 1268-1273 [doi]
- Defeating classical Hardware Countermeasures: a new processing for Side Channel AnalysisDenis Réal, Cécile Canovas, Jessy Clédière, M hamed Drissi, Frédéric Valette. 1274-1279 [doi]
- Power Balanced Gates Insensitive to Routing Capacitance MismatchKonrad J. Kulikowski, Vyas Venkataraman, Zhen Wang, Alexander Taubin. 1280-1285 [doi]
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- FPGA Design for Algebraic Tori-Based Public-Key CryptographyJunfeng Fan, Lejla Batina, Kazuo Sakiyama, Ingrid Verbauwhede. 1292-1297 [doi]
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- Advanced Analog Filters for TelecommunicationsMarcello De Matteis, Stefano D Amico, Andrea Baschirotto. 1316-1321 [doi]
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- Variable Delay of Multi-Gigahertz Digital Signals for Deskew and Jitter-Injection Test ApplicationsDavid C. Keezer, Dany Minier, Patrice Ducharme. 1486-1491 [doi]
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- HOT TOPIC - 3D Integration or How to Scale in the 21st CenturyBruno Bougard, Paul Marchal, Luca Benini, Doris Keitel-Schulz, N. Checka. 1516 [doi]