Table of Contents

• Low-power micromachined microsystems (invited talk)Khalil Najafi. 1-8 [doi]
• Design issues for dynamic voltage scalingThomas D. Burd, Robert W. Brodersen. 9-14 [doi]
• An adaptive on-chip voltage regulation technique for low-power applicationsNicola Dragone, Akshay Aggarwal, L. Richard Carley. 20-24 [doi]
• Robust ultra-low power sub-threshold DTMOS logicHendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul. 25-30 [doi]
• Algorithmic transforms for efficient energy scalable computationAmit Sinha, Alice Wang, Anantha Chandrakasan. 31-36 [doi]
• Operating-system directed power reductionYung-Hsiang Lu, Luca Benini, Giovanni De Micheli. 37-42 [doi]
• Energy minimization with guaranteed quality of serviceGang Qu, Miodrag Potkonjak. 43-49 [doi]
• Energy efficient design of portable wireless systemsTajana Simunic, Haris Vikalo, Peter W. Glynn, Giovanni De Micheli. 49-54 [doi]
• Power consumption reduction in high-speed Sigma-Delta bandpass modulatorsP. Cusinato, F. Stefani, A. Baschirotto. 55-60 [doi]
• Low power mixed analog-digital signal processingMattias Duppils, Christer Svensson. 61-66 [doi]
• A low-power clock and data recovery circuit for 2.5 Gb/s SDH receiversAndrea Pallotta, Francesco Centurelli, Alessandro Trifiletti. 67-72 [doi]
• A micro-power mixed signal IC for battery-operated burglar alarm systemsSilvio Bolliri, Paolo Porcu, Luigi Raffo. 73-77 [doi]
• A recursive algorithm for low-power memory partitioningLuca Benini, Alberto Macii, Massimo Poncino. 78-83 [doi]
• Optimization of high-performance superscalar architectures for energy efficiencyVictor V. Zyuban, Peter M. Kogge. 84-89 [doi]
• dd: a circuit technique to reduce leakage in deep-submicron cache memoriesMichael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy 0001, T. N. Vijaykumar. 90-95 [doi]
• Voltage scheduling in the IpARM microprocessor systemTrevor Pering, Thomas D. Burd, Robert W. Brodersen. 96-101 [doi]
• MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environmentsJason M. Musicer, Jan M. Rabaey. 102-107 [doi]
• Noise-aware power optimization for on-chip interconnectKi-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang. 108-113 [doi]
• New clock-gating techniques for low-power flip-flopsAntonio G. M. Strollo, E. Napoli, Davide De Caro. 114-119 [doi]
• An improved pass transistor synthesis method for low power, high speed CMOS circuitsTudor Vinereanu, Sverre Lidholm. 120-124 [doi]
• Achieving utility arbitrarily close to the optimal with limited energyGang Qu, Miodrag Potkonjak. 125-130 [doi]
• Power minimization of functional units partially guarded computationJunghwan Choi, Jinhwan Jeon, Kiyoung Choi. 131-136 [doi]
• Systematic cycle budget versus system power trade-off: a new perspective on system exploration of real-time data-dominated applicationsErik Brockmeyer, Arnout Vandecappelle, Francky Catthoor. 137-142 [doi]
• Low power sequential circuit design by using priority encoding and clock gatingXunwei Wu, Massoud Pedram. 143-148 [doi]
• Do our low-power tools have enough horse power? (panel session) (title only)Giovanni De Micheli, Tony Correale, Pietro Erratico, Srini Raghvendra, Hugo De Man, Jerry Frankil, Vivek Tiwari. 149 [doi]
• Low-power considerations in the design of bluetooth (invited talk)Sven Mattisson. 151-154 [doi]
• High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologiesMohamed W. Allam, Mohab Anis, Mohamed I. Elmasry. 155-160 [doi]
• A three-port nRERL register file for ultra-low-energy applicationsJun-Ho Kwon, Joonho Lim, Soo-Ik Chae. 161-166 [doi]
• Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertionRaguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl. 167-172 [doi]
• Practical considerations of clock-powered logicWilliam C. Athas. 173-178 [doi]
• Model and analysis for combined package and on-chip power grid simulationRajendran Panda, David Blaauw, Rajat Chaudhry, Vladimir Zolotov, Brian Young, Ravi Ramaraju. 179-184 [doi]
• Cycle-accurate energy consumption measurement and analysis: case study of ARM7TDMINaehyuck Chang, Kwanho Kim, Hyung Gyu Lee. 185-190 [doi]
• Speeding up power estimation of embedded softwareAkshaye Sama, J. F. M. Theeuwen, M. Balakrishnan. 191-196 [doi]
• High-level power estimation with interconnect effectsKavel M. Büyüksahin, Farid N. Najm. 197-202 [doi]
• Cool low power 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session)Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ching-Te Chuang. 203-206 [doi]
• Low-power digital filtering using multiple voltage distribution and adaptive voltage scaling (poster session)Sandeep Dhar, Dragan Maksimovic. 207-209 [doi]
• Low power self-timed Radix-2 division (poster session)Jae-Hee Won, Kiyoung Choi. 210-212 [doi]
• A rate selection algorithm for quantized undithered dynamic supply voltage scaling (poster session)Lama H. Chandrasena, Michael J. Liebelt. 213-215 [doi]
• Low-power sensing and digitization of cardiac signals based on sigma-delta conversion (poster session)Andrea Gerosa, Arianna Novo, Andrea Neviani. 216-218 [doi]
• A 1.5V low-power third order continuous-time lowpass Sigma-Delta A/D converter (poster session)Friedel Gerfers, Yiannos Manoli. 219-221 [doi]
• Design of a low-power CMOS baseband circuit for wideband CDMA testbed (poster session)Chunlei Shi, Yue Wu, Mohammed Ismail. 222-224 [doi]
• A low-voltage CMOS multiplier for RF applications (poster session)Carl James Debono, Franco Maloberti, Joseph Micallef. 225-227 [doi]
• Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session)Koichi Nose, Soo-Ik Chae, Takayasu Sakurai. 228-230 [doi]
• Reducing energy requirements for instruction issue and dispatch in superscalar microprocessors (poster session)Kanad Ghose. 231-233 [doi]
• Low power synthesis of sum-of-products computation (poster session)Kostas Masselos, S. Theoharis, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis. 234-237 [doi]
• A spatially-adaptive bus interface for low-switching communication (poster session)Andrea Acquaviva, Riccardo Scarsi. 238-240 [doi]
• A low power unified cache architecture providing power and performance flexibility (poster session)Afzal Malik, Bill Moyer, Dan Cermak. 241-243 [doi]
• Memory system energy (poster session): influence of hardware-software optimizationsG. Esakkimuthu, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. 244-246 [doi]
• Energy-efficient code generation for DSP56000 family (poster session)Sathishkumar Udayanarayanan, Chaitali Chakrabarti. 247-249 [doi]
• Power-optimal encoding for DRAM address bus (poster session)Wei-Chung Cheng, Massoud Pedram. 250-252 [doi]
• Profile-driven code execution for low power dissipation (poster session)Diana Marculescu. 253-255 [doi]
• An asynchronous matrix-vector multiplier for discrete cosine transformKyeounsoo Kim, Peter A. Beerel, Youpyo Hong. 256-261 [doi]
• Low power techniques and design tradeoffs in adaptive FIR filtering for PRML read channelsKhurram Muhammad, Robert B. Staszewski, Poras T. Balsara. 262-267 [doi]
• Energy-efficient 32 × 32-bit multiplier in tunable near-zero threshold CMOSVjekoslav Svilan, Masataka Matsui, James B. Burr. 268-272 [doi]
• Tradeoffs and design of an ultra low power UHF transceiver integrated in a standard digital CMOS processAlain-Serge Porret, Thierry Melly, Eric A. Vittoz, Christian C. Enz. 273-278 [doi]
• An 8mA, 3.8dB NF, 40dB gain CMOS front-end for GPS applicationsF. Svelto, S. Deantoni, G. Montagna, R. Castello. 279-283 [doi]
• Bias boosting technique for a 1.9GHz class AB RF amplifierTirdad Sowlati, Sifen Luo. 284-288 [doi]
• Analysis and design of low-phase-noise ring oscillatorsLiang Dai, Ramesh Harjani. 289-294 [doi]
• Reliable low-power design in the presence of deep submicron noise (embedded tutorial session)Naresh R. Shanbhag, K. Soumyanath, Samuel Martin. 295-302 [doi]
• Low power DSP s for wireless communications (embedded tutorial session)Ingrid Verbauwhede, Chris Nicol. 303-310 [doi]