Mi-Chang Chang - researchr alias

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Viewing Publication 1 - 11 from 11

2018

Improving ESD protection of 5V NMOSFET large array device in 0.4μm BCD processShao-Chang Huang, Hung-Wei Chen, Jen-Hang Yang, Mi-Chang Chang. mr, 84:48-54, 2018. [doi]

2017

Improving the ESD self-protection capability of 60 V HV p-channel LDMOS large array device in 0.25 μm BCD processHung-Wei Chen, Mi-Chang Chang. mr, 74:110-117, 2017. [doi]

2005

2003

Process and circuit design interlock for application-dependent scaling tradeoffs and optimization in the SoC eraC. H. Diaz, Mi-Chang Chang, Tong-Chern Ong, Jack Yuan-Chen Sun. jssc, 38(3):444-449, 2003. [doi]

2002

High voltage tolerant ESD design for analog applications in deep submicron CMOS technologiesChung-Hui Chen, Yean-Kuen Fang, Chien-Chun Tsai, Shen Tu, Mark K. L. Chen, Mi-Chang Chang. cicc 2002: 89-92 [doi]

Application-dependent scaling tradeoffs and optimization in the SoC eraCarlos H. Diaz, Mi-Chang Chang, Tong-Chern Ong, Jack Yuan-Chen Sun. cicc 2002: 475-478 [doi]

1993

An accurate grid local truncation error for device simulationMi-Chang Chang, Jue-Hsien Chern, Ping Yang. iccad 1993: 275-282 [doi]

Efficient and Robust Path Tracing Algorithm for DC Convergence ProblemMi-Chang Chang, Jue-Hsien Chern, Ping Yang. iscas 1993: 1635-1638

1989

Efficient direct-method parallel circuit simulation using multilevel node tearingMi-Chang Chang. PhD thesis, University of Illinois Urbana-Champaign, USA, 1989. [doi]

1988

iPRIDE: a parallel integrated circuit simulator using direct methodMi-Chang Chang, Ibrahim N. Hajj. iccad 1988: 304-307 [doi]

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