Naohiko Irie - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 13 from 13

2011

Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System IntegrationKiichi Niitsu, Yasufumi Sugimori, Yoshinori Kohama, Kenichi Osada, Naohiko Irie, Hiroki Ishikuro, Tadahiro Kuroda. tvlsi, 19(10):1902-1907, 2011. [doi]

2010

2009

2007

Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCsYusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Yasuhisa Shimazaki, Tadashi Hoshi, Yujiro Miyairi, Toshifumi Ishii, Tetsuya Yamada, Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa, Naohiko Irie. jssc, 42(1):74-83, 2007. [doi]

Embedded SoC Resource Manager to Control Temperature and Data BandwidthMakoto Saen, Kenichi Osada, Satoshi Misaka, Tetsuya Yamada, Yoshitaka Tsujimoto, Yuki Kondo, Tatsuya Kamei, Yutaka Yoshida, Ei Nagahama, Yusuke Nitta, Takayasu Ito, Tadashi Kameyama, Naohiko Irie. isscc 2007: 296-604 [doi]

A Hardware Accelerator for Java:::TM::: Platforms on a 130-nm Embedded Processor CoreTetsuya Yamada, Naohiko Irie, Takanobu Tsunoda, Takahiro Irita, Kenji Kitagawa, Ryohei Yoshida, Keisuke Toyama, Motoaki Satoyama. ieicet, 90-C(2):523-530, 2007. [doi]

A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power ConsumptionYutaka Yoshida, Tatsuya Kamei, Kiyoshi Hayase, Shinichi Shibahara, Osamu Nishii, Toshihiro Hattori, Atsushi Hasegawa, Masashi Takada, Naohiko Irie, Kunio Uchiyama, Toshihiko Odaka, Kiwamu Takada, Keiji Kimura, Hironori Kasahara. isscc 2007: 100-590 [doi]

2006

2005

Elastic shared resource scheduling SOC interconnect architecture for real-time systemMakoto Saen, Hiroshi Ueda, Masaru Hase, Eiji Yamamoto, Yoshihiro Mori, Hiroshi Hatae, Yuki Kondo, Seiji Miura, Itaru Nonomura, Naohiko Irie, Hiromi Watanabe. cicc 2005: 787-790 [doi]

1989

SIMP (Single Instruction stream/Multiple Instruction Pipelining): A Novel High-Speed Single-Processor ArchitectureKazuaki Murakami, Naohiko Irie, Morihiro Kuga, Shinji Tomita. isca 1989: 78-85 [doi]

Sign in or sign up to see more results.

runs on WebDSL