On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation

Xiaoning Qi, Gaofeng Wang, Zhiping Yu, Robert W. Dutton, Tak Young, Norman Chang. On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation. In Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, CICC 2000, Orlando, FL, USA, May 21-24, 2000. pages 487-490, IEEE, 2000. [doi]

Abstract

Abstract is missing.