Luca Crippa - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 9 from 9

2017

Array Architectures for 3-D NAND Flash MemoriesRino Micheloni, Seiichi Aritome, Luca Crippa. pieee, 105(9):1634-1649, 2017. [doi]

Architectural and Integration Options for 3D NAND Flash MemoriesRino Micheloni, Luca Crippa, Cristian Zambelli, Piero Olivo. computers, 6(3):27, 2017. [doi]

2016

Advanced Architectures for 3D NAND Flash Memories with Vertical ChannelLuca Crippa, Rino Micheloni. In Rino Micheloni, editor, 3D Flash Memories. pages 167-195, Springer, 2016. [doi]

3D Charge Trap NAND Flash MemoriesLuca Crippa, Rino Micheloni. In Rino Micheloni, editor, 3D Flash Memories. pages 85-127, Springer, 2016. [doi]

3D Stacked NAND Flash MemoriesRino Micheloni, Luca Crippa. In Rino Micheloni, editor, 3D Flash Memories. pages 63-83, Springer, 2016. [doi]

3D Floating Gate NAND Flash MemoriesRino Micheloni, Luca Crippa. In Rino Micheloni, editor, 3D Flash Memories. pages 129-165, Springer, 2016. [doi]

2006

2003

The flash memory read path: building blocks and critical aspectsRino Micheloni, Luca Crippa, Miriam Sangalli, Giovanni Campardo. pieee, 91(4):537-553, 2003. [doi]

2001

Modular architecture for a family of multilevel 256/192/128/64 Mbit 2-bit/cell 3 V-only NOR flash memory devicesAndrea Silvagni, Stefano Zanardi, Alessandro Manstretta, Marco Scotti, Luca Crippa, Giancarlo Ragone, Giuseppe Fusillo, Giovanni Campardo, Osama Khouri, Marcello Stefanelli. icecsys 2001: 937-940 [doi]

Sign in or sign up to see more results.

runs on WebDSL